at91_pmc.h

00001
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071
00072 #ifndef AT91_PMC_H
00073 #define AT91_PMC_H
00074 
00076 /*\{*/
00077 #define PMC_SCER_OFF                0x00000000  
00078 #define PMC_SCER    (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))   
00079 #define PMC_SCDR_OFF                0x00000004  
00080 #define PMC_SCDR    (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF)))   
00081 #define PMC_SCSR_OFF                0x00000008  
00082 #define PMC_SCSR    (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF)))   
00083 
00084 #define PMC_PCK                              0  
00085 #define PMC_UDP                              7  
00086 #define PMC_PCK0                             8  
00087 #define PMC_PCK1                             9  
00088 #define PMC_PCK2                            10  
00089 /*\}*/
00090
00092 /*\{*/
00093 #define PMC_PCER_OFF                0x00000010  
00094 #define PMC_PCER    (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF)))   
00095 #define PMC_PCDR_OFF                0x00000014  
00096 #define PMC_PCDR    (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF)))   
00097 #define PMC_PCSR_OFF                0x00000018  
00098 #define PMC_PCSR    (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF)))   
00099 /*\}*/
00100
00102 /*\{*/
00103 #define CKGR_MOR_OFF                0x00000020  
00104 #define CKGR_MOR    (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF)))   
00105 
00106 #define CKGR_MOSCEN                          0  
00107 #define CKGR_OSCBYPASS                       1  
00108 #define CKGR_OSCOUNT_MASK           0x0000FF00  
00109 #define CKGR_OSCOUNT_SHIFT                   8  
00110 /*\}*/
00111
00113 /*\{*/
00114 #define CKGR_MCFR_OFF               0x00000024  
00115 #define CKGR_MCFR   (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF)))  
00116 
00117 #define CKGR_MAINF_MASK             0x0000FFFF  
00118 #define CKGR_MAINRDY                        16  
00119 /*\}*/
00120
00122 /*\{*/
00123 #define CKGR_PLLR_OFF               0x0000002C  
00124 #define CKGR_PLLR   (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF)))  
00125 
00126 #define CKGR_DIV_MASK               0x000000FF  
00127 #define CKGR_DIV_SHIFT                       0  
00128 #define CKGR_DIV_0                  0x00000000  
00129 #define CKGR_DIV_BYPASS             0x00000001  
00130 #define CKGR_PLLCOUNT_MASK          0x00003F00  
00131 #define CKGR_PLLCOUNT_SHIFT                  8  
00132 
00133 #define CKGR_OUT_MASK               0x0000C000  
00134 #define CKGR_OUT_0                  0x00000000  
00135 #define CKGR_OUT_1                  0x00004000  
00136 #define CKGR_OUT_2                  0x00008000  
00137 #define CKGR_OUT_3                  0x0000C000  
00138 #define CKGR_MUL_MASK               0x07FF0000  
00139 #define CKGR_MUL_SHIFT                      16  
00140 
00141 #define CKGR_USBDIV_MASK            0x30000000  
00142 #define CKGR_USBDIV_1               0x00000000  
00143 #define CKGR_USBDIV_2               0x10000000  
00144 #define CKGR_USBDIV_4               0x20000000  
00145 /*\}*/
00146
00148 /*\{*/
00149 #define PMC_MCKR_OFF                0x00000030  
00150 #define PMC_MCKR    (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF)))   
00151 
00152 #define PMC_PCKR0_OFF               0x00000040  
00153 #define PMC_PCKR0   (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF)))  
00154 #define PMC_PCKR1_OFF               0x00000044  
00155 #define PMC_PCKR1   (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF)))  
00156 #define PMC_PCKR2_OFF               0x00000048  
00157 #define PMC_PCKR2   (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF)))  
00158 
00159 #define PMC_CSS_MASK                0x00000003  
00160 #define PMC_CSS_SLOW_CLK            0x00000000  
00161 #define PMC_CSS_MAIN_CLK            0x00000001  
00162 #define PMC_CSS_PLL_CLK             0x00000003  
00163 
00164 #define PMC_PRES_MASK               0x0000001C  
00165 #define PMC_PRES_SHIFT                       2   
00166 #define PMC_PRES_CLK                0x00000000  
00167 #define PMC_PRES_CLK_2              0x00000004  
00168 #define PMC_PRES_CLK_4              0x00000008  
00169 #define PMC_PRES_CLK_8              0x0000000C  
00170 #define PMC_PRES_CLK_16             0x00000010  
00171 #define PMC_PRES_CLK_32             0x00000014  
00172 #define PMC_PRES_CLK_64             0x00000018  
00173 /*\}*/
00174
00176 /*\{*/
00177 #define PMC_IER_OFF                 0x00000060  
00178 #define PMC_IER     (*((reg32_t *)(PMC_BASE + PMC_IER_OFF)))    
00179 #define PMC_IDR_OFF                 0x00000064  
00180 #define PMC_IDR     (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF)))    
00181 #define PMC_SR_OFF                  0x00000068  
00182 #define PMC_SR      (*((reg32_t *)(PMC_BASE + PMC_SR_OFF)))     
00183 #define PMC_IMR_OFF                 0x0000006C  
00184 #define PMC_IMR     (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF)))    
00185 
00186 #define PMC_MOSCS                            0  
00187 #define PMC_LOCK                             2  
00188 #define PMC_MCKRDY                           3  
00189 #define PMC_PCKRDY0                          8  
00190 #define PMC_PCKRDY1                          9  
00191 #define PMC_PCKRDY2                         10  
00192 /*\}*/
00193
00194 #endif /* AT91_PMC_H */