Go to the source code of this file.
Defines | |
| #define | TWI_CR_OFF 0x00000000 |
| TWI Control Register. | |
| #define | TWI_CR (*((reg32_t *)(TWI_BASE + TWI_CR_OFF))) |
| Control register address. | |
| #define | TWI_START 0 |
| Send start condition. | |
| #define | TWI_STOP 1 |
| Send stop condition. | |
| #define | TWI_MSEN 2 |
| Enable master mode. | |
| #define | TWI_MSDIS 3 |
| Disable master mode. | |
| #define | TWI_SWRST 7 |
| Software reset. | |
| #define | TWI_MMR_OFF 0x00000004 |
| TWI Master Mode Register. | |
| #define | TWI_MMR (*((reg32_t *)(TWI_BASE + TWI_MMR_OFF))) |
| Master mode register address. | |
| #define | TWI_IADRSZ_SHIFT 8 |
| Internal device address size shift. | |
| #define | TWI_IADRSZ 0x00000300 |
| Internal device address size mask. | |
| #define | TWI_IADRSZ_NONE 0x00000000 |
| No internal device address. | |
| #define | TWI_IADRSZ_1BYTE 0x00000100 |
| One byte internal device address. | |
| #define | TWI_IADRSZ_2BYTE 0x00000200 |
| Two byte internal device address. | |
| #define | TWI_IADRSZ_3BYTE 0x00000300 |
| Three byte internal device address. | |
| #define | TWI_MREAD 12 |
| Master read direction. | |
| #define | TWI_DADR 0x007F0000 |
| Device address mask. | |
| #define | TWI_DADR_SHIFT 16 |
| Device address LSB. | |
| #define | TWI_IADR_OFF 0x0000000C |
| TWI Internal Address Register. | |
| #define | TWI_IADR (*((reg32_t *)(TWI_BASE + TWI_IADR_OFF))) |
| Internal address register address. | |
| #define | TWI_IADR_MASK 0x00FFFFFF |
| Internal address mask. | |
| #define | TWI_IADR_SHIFT 0 |
| Internal address LSB. | |
| #define | TWI_CWGR_OFF 0x00000010 |
| TWI Clock Waveform Generator Register. | |
| #define | TWI_CWGR (*((reg32_t *)(TWI_BASE + TWI_CWGR_OFF))) |
| Clock waveform generator register address. | |
| #define | TWI_CLDIV 0x000000FF |
| Clock low divider mask. | |
| #define | TWI_CLDIV_SHIFT 0 |
| Clock low divider LSB. | |
| #define | TWI_CHDIV 0x0000FF00 |
| Clock high divider mask. | |
| #define | TWI_CHDIV_SHIFT 8 |
| Clock high divider LSB. | |
| #define | TWI_CKDIV 0x00070000 |
| Clock divider mask. | |
| #define | TWI_CKDIV_SHIFT 16 |
| Clock divider LSB. | |
| #define | TWI_SR_OFF 0x00000020 |
| TWI Status and Interrupt Registers. | |
| #define | TWI_SR (*((reg32_t *)(TWI_BASE + TWI_SR_OFF))) |
| Status register address. | |
| #define | TWI_IER_OFF 0x00000024 |
| Interrupt enable register offset. | |
| #define | TWI_IER (*((reg32_t *)(TWI_BASE + TWI_IER_OFF))) |
| Interrupt enable register address. | |
| #define | TWI_IDR_OFF 0x00000028 |
| Interrupt disable register offset. | |
| #define | TWI_IDR (*((reg32_t *)(TWI_BASE + TWI_IDR_OFF))) |
| Interrupt disable register address. | |
| #define | TWI_IMR_OFF 0x0000002C |
| Interrupt mask register offset. | |
| #define | TWI_IMR (*((reg32_t *)(TWI_BASE + TWI_IMR_OFF))) |
| Interrupt mask register address. | |
| #define | TWI_TXCOMP 0 |
| Transmission completed. | |
| #define | TWI_RXRDY 1 |
| Receive holding register ready. | |
| #define | TWI_TXRDY 2 |
| Transmit holding register ready. | |
| #define | TWI_NACK 8 |
| Not acknowledged. | |
| #define | TWI_RHR_OFF 0x00000030 |
| TWI Receive Holding Register. | |
| #define | TWI_RHR (*((reg32_t *)(TWI_BASE + TWI_RHR_OFF))) |
| Receive holding register address. | |
| #define | TWI_THR_OFF 0x00000034 |
| TWI Transmit Holding Register. | |
| #define | TWI_THR (*((reg32_t *)(TWI_BASE + TWI_THR_OFF))) |
| Transmit holding register address. | |
Detailed Description
AT91SAM7 Two wire interface. This file is based on NUT/OS implementation. See license below.
Definition in file at91_twi.h.
Define Documentation
| #define TWI_CR_OFF 0x00000000 |
| #define TWI_CWGR_OFF 0x00000010 |
TWI Clock Waveform Generator Register.
Clock waveform generator register offset.
Definition at line 124 of file at91_twi.h.
| #define TWI_IADR_OFF 0x0000000C |
TWI Internal Address Register.
Internal address register offset.
Definition at line 114 of file at91_twi.h.
| #define TWI_MMR_OFF 0x00000004 |
| #define TWI_RHR_OFF 0x00000030 |
TWI Receive Holding Register.
Receive holding register offset.
Definition at line 177 of file at91_twi.h.
| #define TWI_SR_OFF 0x00000020 |
TWI Status and Interrupt Registers.
Status register offset.
Definition at line 138 of file at91_twi.h.
| #define TWI_THR_OFF 0x00000034 |
TWI Transmit Holding Register.
Transmit holding register offset.
Definition at line 185 of file at91_twi.h.
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