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at91sam7.h
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00001 00041 /* 00042 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved. 00043 * 00044 * Redistribution and use in source and binary forms, with or without 00045 * modification, are permitted provided that the following conditions 00046 * are met: 00047 * 00048 * 1. Redistributions of source code must retain the above copyright 00049 * notice, this list of conditions and the following disclaimer. 00050 * 2. Redistributions in binary form must reproduce the above copyright 00051 * notice, this list of conditions and the following disclaimer in the 00052 * documentation and/or other materials provided with the distribution. 00053 * 3. Neither the name of the copyright holders nor the names of 00054 * contributors may be used to endorse or promote products derived 00055 * from this software without specific prior written permission. 00056 * 00057 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00058 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00059 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00060 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00061 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00062 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00063 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00064 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00065 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00066 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00067 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00068 * SUCH DAMAGE. 00069 * 00070 * For additional information see http://www.ethernut.de/ 00071 */ 00072 00073 #ifndef AT91SAM7_H 00074 #define AT91SAM7_H 00075 00076 #include <cfg/compiler.h> 00077 00078 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE 00079 #define FLASH_BASE 0x100000UL 00080 #define RAM_BASE 0x200000UL 00081 00082 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address. 00083 #define UDP_BASE 0xFFFB0000 ///< USB device port base address. 00084 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address. 00085 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address. 00086 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address. 00087 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address. 00088 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address. 00089 #define ADC_BASE 0xFFFD8000 ///< ADC base address. 00090 00091 #define AIC_BASE 0xFFFFF000 ///< AIC base address. 00092 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address. 00093 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address. 00094 #define PMC_BASE 0xFFFFFC00 ///< PMC base address. 00095 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address. 00096 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address. 00097 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address. 00098 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address. 00099 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address. 00100 #define MC_BASE 0xFFFFFF00 ///< Memory controller base. 00101 00102 #if CPU_ARM_SAM7X 00103 #define CAN_BASE 0xFFFD0000 ///< PWM controller base address. 00104 #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address. 00105 #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address. 00106 #define SPI1_BASE 0xFFFE4000 ///< SPI1 base address. 00107 #define PIOB_BASE 0xFFFFF600 ///< PIO base address. 00108 #endif 00109 00110 #if CPU_ARM_SAM7S_LARGE 00111 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address. 00112 #endif 00113 00114 #define PIO_HAS_MULTIDRIVER 1 00115 #define PIO_HAS_PULLUP 1 00116 #define PIO_HAS_PERIPHERALSELECT 1 00117 #define PIO_HAS_OUTPUTWRITEENABLE 1 00118 00119 #define DBGU_HAS_PDC 1 00120 #define SPI_HAS_PDC 1 00121 #define SSC_HAS_PDC 1 00122 #define USART_HAS_PDC 1 00123 00124 /* PDC registers */ 00125 #define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register. 00126 #define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register. 00127 #define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register. 00128 #define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register. 00129 #define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register. 00130 #define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register. 00131 #define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register. 00132 #define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register. 00133 #define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register. 00134 #define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register. 00135 00136 #define PDC_RXTEN 0 00137 #define PDC_RXTDIS 1 00138 #define PDC_TXTEN 8 00139 #define PDC_TXTDIS 9 00140 00141 #else 00142 #error No base address register definition for selected ARM CPU 00143 00144 #endif 00145 00146 #if CPU_ARM_AT91SAM7S64 00147 #define FLASH_MEM_SIZE 0x10000UL ///< Internal flash memory size 00148 #define FLASH_PAGE_SIZE_BYTES 128 ///< Size of cpu flash memory page in bytes 00149 #define FLASH_BANKS_NUM 1 ///< Number of flash banks 00150 #define FLASH_SECTORS_NUM 16 ///< Number of flash sector 00151 #define FLASH_PAGE_PER_SECTOR 32 ///< Number of page for sector 00152 00153 #elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128 00154 #define FLASH_MEM_SIZE 0x20000UL ///< Internal flash memory size 00155 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00156 #define FLASH_BANKS_NUM 1 ///< Number of flash banks 00157 #define FLASH_SECTORS_NUM 8 ///< Number of flash sector 00158 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector 00159 00160 #elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 00161 #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size 00162 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00163 #define FLASH_BANKS_NUM 1 ///< Number of flash banks 00164 #define FLASH_SECTORS_NUM 16 ///< Number of flash sector 00165 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector 00166 00167 #elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512 00168 #define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size 00169 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00170 #define FLASH_BANKS_NUM 2 ///< Number of flash banks 00171 #define FLASH_SECTORS_NUM 32 ///< Number of flash sector 00172 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector 00173 00174 #else 00175 #error Memory size definition for selected ARM CPU 00176 #endif 00177 00178 #include "at91_aic.h" 00179 #include "at91_pit.h" 00180 #include "at91_pmc.h" 00181 #include "at91_mc.h" 00182 #include "at91_wdt.h" 00183 #include "at91_rstc.h" 00184 #include "at91_pio.h" 00185 #include "at91_us.h" 00186 #include "at91_dbgu.h" 00187 #include "at91_tc.h" 00188 #include "at91_adc.h" 00189 #include "at91_pwm.h" 00190 #include "at91_spi.h" 00191 #include "at91_twi.h" 00192 #include "at91_ssc.h" 00193 #include "at91_emac.h" 00194 //TODO: add other peripherals 00195 00200 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE 00201 #define FIQ_ID 0 ///< Fast interrupt ID. 00202 #define SYSC_ID 1 ///< System controller interrupt. 00203 #define US0_ID 6 ///< USART 0 ID. 00204 #define US1_ID 7 ///< USART 1 ID. 00205 #define SSC_ID 8 ///< Synchronous serial controller ID. 00206 #define TWI_ID 9 ///< Two-wire interface ID. 00207 #define PWMC_ID 10 ///< PWM controller ID. 00208 #define UDP_ID 11 ///< USB device port ID. 00209 #define TC0_ID 12 ///< Timer 0 ID. 00210 #define TC1_ID 13 ///< Timer 1 ID. 00211 #define TC2_ID 14 ///< Timer 2 ID. 00212 00213 #define IRQ0_ID 30 ///< External interrupt 0 ID. 00214 #define IRQ1_ID 31 ///< External interrupt 1 ID. 00215 00216 #if CPU_ARM_SAM7X 00217 #define PIOA_ID 2 ///< Parallel A I/O controller ID. 00218 #define PIOB_ID 3 ///< Parallel B I/O controller ID. 00219 #define SPI0_ID 4 ///< Serial peripheral interface 0 ID. 00220 #define SPI1_ID 5 ///< Serial peripheral interface 1 ID. 00221 #define CAN_ID 15 ///< CAN controller ID. 00222 #define EMAC_ID 16 ///< Ethernet MAC ID. 00223 #define ADC_ID 17 ///< Analog to digital converter ID. 00224 /* 18-29 Reserved */ 00225 00226 #endif 00227 00228 #if CPU_ARM_SAM7S_LARGE 00229 #define PIOA_ID 2 ///< Parallel I/O controller ID. 00230 /* ID 3 is reserved */ 00231 #define ADC_ID 4 ///< Analog to digital converter ID. 00232 #define SPI_ID 5 ///< Serial peripheral interface ID. 00233 #define SPI0_ID SPI_ID ///< Alias 00234 #endif 00235 00236 #else 00237 #error No peripheral ID and interrupts definition for selected ARM CPU 00238 00239 #endif 00240 /*\}*/ 00241 00246 #if CPU_ARM_SAM7S_LARGE 00247 #define RXD0 5 00248 #define TXD0 6 00249 #define RXD1 21 00250 #define TXD1 22 00251 #define DTXD 10 00252 #define DRXD 9 00253 #elif CPU_ARM_SAM7X 00254 #define RXD0 0 // PA0 00255 #define TXD0 1 // PA1 00256 #define RXD1 5 // PA5 00257 #define TXD1 6 // PA6 00258 #define DTXD 28 // PA28 00259 #define DRXD 27 // PA27 00260 #else 00261 #error No USART & debug pin names definition for selected ARM CPU 00262 #endif 00263 /*\}*/ 00264 00269 #if CPU_ARM_SAM7S_LARGE 00270 #define SPI0_NPCS0 11 // Same as NSS pin. 00271 #define SPI0_MISO 12 00272 #define SPI0_MOSI 13 00273 #define SPI0_SPCK 14 00274 00275 #elif CPU_ARM_SAM7X 00276 #define SPI0_NPCS0 12 // Same as NSS pin. PA12 00277 #define SPI0_NPCS1 13 // PA13 00278 #define SPI0_NPCS2 14 // PA14 00279 #define SPI0_NPCS3 15 // PA15 00280 #define SPI0_MISO 16 // PA16 00281 #define SPI0_MOSI 17 // PA17 00282 #define SPI0_SPCK 18 // PA18 00283 00284 #define SPI1_NPCS0 21 // Same as NSS pin. PA21 00285 #define SPI1_NPCS1 25 // PA25 00286 #define SPI1_NPCS2 26 // PA26 00287 #define SPI1_NPCS3 29 // PA29 00288 #define SPI1_MISO 24 // PA24 00289 #define SPI1_MOSI 23 // PA23 00290 #define SPI1_SPCK 22 // PA22 00291 00292 #else 00293 #error No SPI pins name definition for selected ARM CPU 00294 00295 #endif 00296 /*\}*/ 00297 00302 #if CPU_ARM_SAM7S_LARGE 00303 00304 #define SSC_TF 15 // PA15 00305 #define SSC_TK 16 // PA16 00306 #define SSC_TD 17 // PA17 00307 #define SSC_RD 18 // PA18 00308 #define SSC_RK 19 // PA19 00309 #define SSC_RF 20 // PA20 00310 00311 #elif CPU_ARM_SAM7X 00312 00313 #define SSC_TF 21 // PA21 00314 #define SSC_TK 22 // PA22 00315 #define SSC_TD 23 // PA23 00316 #define SSC_RD 24 // PA24 00317 #define SSC_RK 25 // PA25 00318 #define SSC_RF 26 // PA26 00319 00320 #else 00321 #error No SSC pins name definition for selected ARM CPU 00322 00323 #endif 00324 /*\}*/ 00325 00330 #if CPU_ARM_SAM7X 00331 #define TIOA0 23 // PB23 00332 #define TIOB0 24 // PB24 00333 #define TIOA1 25 // PB25 00334 #define TIOB1 26 // PB26 00335 #define TIOA2 27 // PB27 00336 #define TIOB2 28 // PB28 00337 00338 #define TIO_PIO_PDR PIOB_PDR 00339 #define TIO_PIO_ABSR PIOB_ASR 00340 00341 #elif CPU_ARM_SAM7S_LARGE 00342 #define TIOA0 0 // PA0 00343 #define TIOB0 1 // PA1 00344 #define TIOA1 15 // PA15 00345 #define TIOB1 16 // PA16 00346 #define TIOA2 26 // PA26 00347 #define TIOB2 27 // PA27 00348 00349 #define TIO_PIO_PDR PIOA_PDR 00350 #define TIO_PIO_ABSR PIOA_BSR 00351 00352 #else 00353 #error No Timer Counter names of pins definition for selected ARM CPU 00354 00355 #endif 00356 /*\}*/ 00357 00358 00363 #if CPU_ARM_SAM7X 00364 #define PWM0 19 // PB19 00365 #define PWM1 20 // PB20 00366 #define PWM2 21 // PB21 00367 #define PWM3 22 // PB22 00368 00369 #define PWM_PIO_PDR PIOB_PDR 00370 #define PWM_PIO_PER PIOB_PER 00371 #define PWM_PIO_CODR PIOB_CODR 00372 #define PWM_PIO_SODR PIOB_SODR 00373 #define PWM_PIO_OER PIOB_OER 00374 #define PWM_PIO_ABSR PIOB_ASR 00375 00376 #elif CPU_ARM_SAM7S_LARGE 00377 #define PWM0 11 // PA11 00378 #define PWM1 12 // PA12 00379 #define PWM2 13 // PA13 00380 #define PWM3 14 // PA14 00381 00382 #define PWM_PIO_PDR PIOA_PDR 00383 #define PWM_PIO_PER PIOA_PER 00384 #define PWM_PIO_CODR PIOA_CODR 00385 #define PWM_PIO_SODR PIOA_SODR 00386 #define PWM_PIO_OER PIOA_OER 00387 #define PWM_PIO_ABSR PIOA_BSR 00388 00389 #else 00390 #error No PWM names of pins definition for selected ARM CPU 00391 00392 #endif 00393 /*\}*/ 00394 00399 #if CPU_ARM_SAM7X 00400 #define TWD 10 00401 #define TWCK 11 00402 00403 #elif CPU_ARM_SAM7S_LARGE 00404 #define TWD 3 //PA3 00405 #define TWCK 4 //PA4 00406 00407 #else 00408 #error No TWI names of pins definition for selected ARM CPU 00409 #endif 00410 00415 #if CPU_ARM_SAM7X 00416 #define ADTRG 18 // PB18 00417 #define AD0 23 // PB27 00418 #define AD1 24 // PB28 00419 #define AD2 25 // PB29 00420 #define AD3 26 // PB30 00421 00422 #elif CPU_ARM_SAM7S_LARGE 00423 #define ADTRG 18 // PA8 00424 #define AD0 0 // PA17 00425 #define AD1 1 // PA18 00426 #define AD2 15 // PA19 00427 #define AD3 16 // PA20 00428 00429 #else 00430 #error No ADC names of pins definition for selected ARM CPU 00431 00432 #endif 00433 /*\}*/ 00434 00435 00439 #if CPU_ARM_SAM7X 00440 #define PHY_TXCLK_BIT BV(0) 00441 #define PHY_TXEN_BIT BV(1) 00442 #define PHY_TXD0_BIT BV(2) 00443 #define PHY_TXD1_BIT BV(3) 00444 #define PHY_CRS_BIT BV(4) 00445 #define PHY_RXD0_BIT BV(5) 00446 #define PHY_RXD1_BIT BV(6) 00447 #define PHY_RXER_BIT BV(7) 00448 #define PHY_MDC_BIT BV(8) 00449 #define PHY_MDIO_BIT BV(9) 00450 #define PHY_TXD2_BIT BV(10) 00451 #define PHY_TXD3_BIT BV(11) 00452 #define PHY_TXER_BIT BV(12) 00453 #define PHY_RXD2_BIT BV(13) 00454 #define PHY_RXD3_BIT BV(14) 00455 #define PHY_RXDV_BIT BV(15) 00456 #define PHY_COL_BIT BV(16) 00457 #define PHY_RXCLK_BIT BV(17) 00458 00459 #elif CPU_ARM_SAM7S_LARGE 00460 /* No ethernet interface is present on this cpu */ 00461 #else 00462 #error No MII/RMII PHY pins interface was define for select CPU. 00463 #endif 00464 00465 #define PHY_MII_PINS \ 00466 ( PHY_TXEN_BIT \ 00467 | PHY_TXD0_BIT \ 00468 | PHY_TXD1_BIT \ 00469 | PHY_CRS_BIT \ 00470 | PHY_RXD0_BIT \ 00471 | PHY_RXD1_BIT \ 00472 | PHY_RXER_BIT \ 00473 | PHY_MDC_BIT \ 00474 | PHY_MDIO_BIT \ 00475 | PHY_TXD2_BIT \ 00476 | PHY_TXD3_BIT \ 00477 | PHY_TXER_BIT \ 00478 | PHY_RXD2_BIT \ 00479 | PHY_RXD3_BIT \ 00480 | PHY_RXDV_BIT \ 00481 | PHY_COL_BIT \ 00482 | PHY_RXCLK_BIT) 00483 // \} 00484 00485 #endif /* AT91SAM7_H */
