00001
00038 #ifndef CFG_SER_H
00039 #define CFG_SER_H
00040 
00052 #define CONFIG_UART0_ENABLED 1
00053 
00059 #define CONFIG_UART0_TXBUFSIZE  32
00060 
00066 #define CONFIG_UART0_RXBUFSIZE  32
00067 
00073 #define CONFIG_UART1_ENABLED 1
00074 
00081 #define CONFIG_UART1_TXBUFSIZE  32
00082 
00089 #define CONFIG_UART1_RXBUFSIZE  32
00090 
00096 #define CONFIG_UART2_ENABLED 1
00097 
00104 #define CONFIG_UART2_TXBUFSIZE  32
00105 
00112 #define CONFIG_UART2_RXBUFSIZE  32
00113 
00119 #define CONFIG_UART3_ENABLED 1
00120 
00127 #define CONFIG_UART3_TXBUFSIZE  32
00128 
00135 #define CONFIG_UART3_RXBUFSIZE  32
00136 
00142 #define CONFIG_UART4_ENABLED 1
00143 
00150 #define CONFIG_UART4_TXBUFSIZE  32
00151 
00158 #define CONFIG_UART4_RXBUFSIZE  32
00159 
00165 #define CONFIG_UART5_ENABLED 1
00166 
00173 #define CONFIG_UART5_TXBUFSIZE  32
00174 
00181 #define CONFIG_UART5_RXBUFSIZE  32
00182 
00188 #define CONFIG_UART6_ENABLED 1
00189 
00196 #define CONFIG_UART6_TXBUFSIZE  32
00197 
00204 #define CONFIG_UART6_RXBUFSIZE  32
00205 
00211 #define CONFIG_UART7_ENABLED 1
00212 
00219 #define CONFIG_UART7_TXBUFSIZE  32
00220 
00227 #define CONFIG_UART7_RXBUFSIZE  32
00228 
00235 #define CONFIG_SPI_TXBUFSIZE    32
00236 
00243 #define CONFIG_SPI_RXBUFSIZE    32
00244 
00251 #define CONFIG_SPI0_TXBUFSIZE   32
00252 
00259 #define CONFIG_SPI0_RXBUFSIZE   32
00260 
00267 #define CONFIG_SPI1_TXBUFSIZE   32
00268 
00275 #define CONFIG_SPI1_RXBUFSIZE   32
00276 
00284 #define CONFIG_SPI_DATA_ORDER   SER_MSB_FIRST
00285 
00291 #define CONFIG_SPI_CLOCK_DIV    16
00292 
00299 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
00300 
00308 #define CONFIG_SPI_CLOCK_PHASE      SPI_SAMPLE_ON_FIRST_EDGE
00309 
00315 #define CONFIG_SER_TXTIMEOUT    -1
00316 
00322 #define CONFIG_SER_RXTIMEOUT    -1
00323 
00329 #define CONFIG_SER_HWHANDSHAKE   0
00330 
00336 #define CONFIG_SER_DEFBAUDRATE   0UL
00337 
00339 #define CONFIG_SER_STROBE        0
00340 
00341 #endif /* CFG_SER_H */