00001
00038 #ifndef DRV_HSMCI_SAM3_H
00039 #define DRV_HSMCI_SAM3_H
00040 
00041 #include <cfg/macros.h>
00042 #include <cfg/debug.h>
00043
00044 #include <io/cm3.h>
00045
00046 #define HSMCI_CHECK_BUSY() \
00047     do { \
00048         cpu_relax(); \
00049     } while (!(HSMCI_SR & BV(HSMCI_SR_NOTBUSY)))
00050 
00051
00052 #define HSMCI_INIT_SPEED  400000
00053 #define HSMCI_HIGH_SPEED  21000000
00054 
00055 #define HSMCI_HS_MODE     BV(0)
00056 
00057 typedef struct Hsmci
00058 {
00059 } Hsmci;
00060
00061 INLINE void hsmci_enableIrq(void)
00062 {
00063     HSMCI_IER = BV(HSMCI_IER_RTOE);
00064 }
00065
00066 INLINE void hsmci_disableIrq(void)
00067 {
00068     HSMCI_IDR = BV(HSMCI_IER_RTOE);
00069 }
00070
00071 INLINE void hsmci_setBusWidth(size_t len)
00072 {
00073     int sdcsel= 0;
00074     if (len == 4)
00075         sdcsel = 2;
00076     if (len == 8)
00077         sdcsel = 3;
00078
00079     HSMCI_SDCR = (sdcsel << HSMCI_SDCR_SDCBUS_SHIFT) & HSMCI_SDCR_SDCBUS_MASK;
00080 }
00081
00082 void hsmci_readResp(uint32_t *resp, size_t len);
00083 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type);
00084
00085 void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size);
00086 void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size);
00087 void hsmci_waitTransfer(void);
00088
00089 void hsmci_setSpeed(uint32_t data_rate, int flag);
00090
00091
00092 void hsmci_init(Hsmci *hsmci);
00093
00094 #endif /* DRV_HSMCI_SAM3_H */