00001
00048 #ifndef DRV_I2S_H
00049 #define DRV_I2S_H
00050 
00051 #warning __FILTER_NEXT_WARNING__
00052 #warning This API is ALPHA! we could change it..
00053 
00054 #include <cfg/compiler.h>
00055 #include <cfg/debug.h>
00056 #include <cfg/macros.h>
00057
00058 #include <cpu/attr.h>
00059
00060 #include CPU_HEADER(i2s)
00061 
00062 struct I2sContext;
00063 struct I2s;
00064
00065 typedef int (*i2s_write_t) (struct I2s *i2s, uint32_t sample);
00066 typedef uint32_t (*i2s_read_t) (struct I2s *i2s);
00067 typedef void (*i2s_dma_tx_buf_t) (struct I2s *i2s, void *buf, size_t len);
00068 typedef void (*i2s_dma_rx_buf_t) (struct I2s *i2s, void *buf, size_t len);
00069 typedef bool (*i2s_dma_tx_is_finished_t) (struct I2s *i2s);
00070 typedef bool (*i2s_dma_rx_is_finished_t) (struct I2s *i2s);
00071 typedef void (*i2s_dma_callback_t) (struct I2s *i2s, void *_buf, size_t len);
00072 typedef void (*i2s_dma_start_streaming_t) (struct I2s *i2s, void *buf, size_t len, size_t slice_len);
00073 typedef void (*i2s_dma_wait_t) (struct I2s *i2s);
00074 typedef void (*i2s_dma_stop_t) (struct I2s *i2s);
00075
00076 typedef struct I2sContext
00077 {
00078     i2s_write_t                write;
00079     i2s_dma_tx_buf_t           tx_buf;
00080     i2s_dma_tx_is_finished_t   tx_isFinish;
00081     i2s_dma_callback_t         tx_callback;
00082     i2s_dma_start_streaming_t  tx_start;
00083     i2s_dma_wait_t             tx_wait;
00084     i2s_dma_stop_t             tx_stop;
00085     size_t tx_slice_len;
00086
00087     i2s_read_t                 read;
00088     i2s_dma_rx_buf_t           rx_buf;
00089     i2s_dma_rx_is_finished_t   rx_isFinish;
00090     i2s_dma_callback_t         rx_callback;
00091     i2s_dma_start_streaming_t  rx_start;
00092     i2s_dma_wait_t             rx_wait;
00093     i2s_dma_stop_t             rx_stop;
00094     size_t rx_slice_len;
00095
00096     DB(id_t _type);
00097
00098 } I2sContext;
00099
00100 typedef struct I2s
00101 {
00102     I2sContext ctx;
00103     struct I2sHardware *hw;
00104 } I2s;
00105
00106 INLINE int i2s_write(I2s *i2s, uint32_t sample)
00107 {
00108     ASSERT(i2s->ctx.write);
00109     return i2s->ctx.write(i2s, sample);
00110 }
00111
00112
00113 INLINE uint32_t i2s_read(I2s *i2s)
00114 {
00115     ASSERT(i2s->ctx.read);
00116     return i2s->ctx.read(i2s);
00117 }
00118
00119 /*
00120  * Check if a dma transfer is finished.
00121  *
00122  * Useful for kernel-less applications.
00123  */
00124 INLINE bool i2s_dmaTxIsFinished(I2s *i2s)
00125 {
00126     ASSERT(i2s->ctx.tx_isFinish);
00127     return i2s->ctx.tx_isFinish(i2s);
00128 }
00129
00130 INLINE bool i2s_dmaRxIsFinished(I2s *i2s)
00131 {
00132     ASSERT(i2s->ctx.rx_isFinish);
00133     return i2s->ctx.rx_isFinish(i2s);
00134 }
00135
00136 INLINE void i2s_dmaTxBuffer(I2s *i2s, void *buf, size_t len)
00137 {
00138     ASSERT(i2s->ctx.tx_buf);
00139     i2s->ctx.tx_buf(i2s, buf, len);
00140 }
00141
00142 INLINE void i2s_dmaRxBuffer(I2s *i2s, void *buf, size_t len)
00143 {
00144     ASSERT(i2s->ctx.rx_buf);
00145     i2s->ctx.rx_buf(i2s, buf, len);
00146 }
00147
00148
00149 INLINE void i2s_dmaTxWait(I2s *i2s)
00150 {
00151     ASSERT(i2s->ctx.tx_wait);
00152     i2s->ctx.tx_wait(i2s);
00153 }
00154
00155
00156 INLINE void i2s_dmaStartTxStreaming(I2s *i2s, void *buf, size_t len, size_t slice_len, i2s_dma_callback_t callback)
00157 {
00158     ASSERT(i2s->ctx.tx_start);
00159     ASSERT(len % slice_len == 0);
00160     ASSERT(callback);
00161
00162     i2s->ctx.tx_callback = callback;
00163     i2s->ctx.tx_slice_len = slice_len;
00164     i2s->ctx.tx_start(i2s, buf, len, slice_len);
00165 }
00166
00167 INLINE void i2s_dmaTxStop(I2s *i2s)
00168 {
00169     ASSERT(i2s->ctx.tx_stop);
00170     i2s->ctx.tx_stop(i2s);
00171 }
00172
00173 INLINE void i2s_dmaStartRxStreaming(I2s *i2s, void *buf, size_t len, size_t slice_len, i2s_dma_callback_t callback)
00174 {
00175     ASSERT(i2s->ctx.rx_start);
00176     ASSERT(len % slice_len == 0);
00177     ASSERT(callback);
00178
00179     i2s->ctx.rx_callback = callback;
00180     i2s->ctx.rx_slice_len = slice_len;
00181     i2s->ctx.rx_start(i2s, buf, len, slice_len);
00182 }
00183
00184 INLINE void i2s_dmaRxStop(I2s *i2s)
00185 {
00186     ASSERT(i2s->ctx.rx_stop);
00187     i2s->ctx.rx_stop(i2s);
00188 }
00189
00190 void i2s_init(I2s *i2s, int channel);
00191  //defgroup i2s
00193 #endif /* DRV_I2S_H */