00001
00039 #include "hw/hw_i2s.h"
00040
00041 #include "cfg/cfg_i2s.h"
00042
00043 // Define log settings for cfg/log.h.
00044 #define LOG_LEVEL         I2S_LOG_LEVEL
00045 #define LOG_FORMAT        I2S_LOG_FORMAT
00046 #include <cfg/log.h>
00047
00048 #include <drv/timer.h>
00049 #include <drv/i2s.h>
00050 #include <drv/dmac_sam3.h>
00051
00052 #include <mware/event.h>
00053
00054 #include <cpu/irq.h>
00055
00056 #include <io/cm3.h>
00057
00058 #include <string.h>
00059
00060
00061 #define I2S_DMAC_CH    0
00062 #define I2S_CACHED_CHUNK_SIZE 2
00063 
00064
00065 #define I2S_TX_DMAC_CFG  (BV(DMAC_CFG_DST_H2SEL) | \
00066                           BV(DMAC_CFG_SOD) | \
00067                         ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
00068                          (4 & DMAC_CFG_SRC_PER_MASK))
00069 
00070 #define I2S_TX_DMAC_CTRLB  (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
00071                             DMAC_CTRLB_DST_INCR_FIXED | \
00072                             DMAC_CTRLB_SRC_INCR_INCREMENTING)
00073 
00074
00075 #define I2S_RX_DMAC_CFG  (BV(DMAC_CFG_SRC_H2SEL) | \
00076                           BV(DMAC_CFG_SOD) | \
00077                         ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
00078                          (4 & DMAC_CFG_SRC_PER_MASK))
00079 
00080 #define I2S_RX_DMAC_CTRLB  (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
00081                             DMAC_CTRLB_DST_INCR_INCREMENTING | \
00082                             DMAC_CTRLB_SRC_INCR_FIXED)
00083 
00084
00085 #if CONFIG_WORD_BIT_SIZE == 32
00086     #define I2S_TX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_WORD | \
00087                                 DMAC_CTRLA_DST_WIDTH_WORD)
00088     #define I2S_RX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_WORD | \
00089                                 DMAC_CTRLA_DST_WIDTH_WORD)
00090     #define I2S_WORD_BYTE_SIZE      4
00091 #elif CONFIG_WORD_BIT_SIZE == 16
00092 
00093     #define I2S_TX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
00094                                 DMAC_CTRLA_DST_WIDTH_HALF_WORD)
00095     #define I2S_RX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
00096                                 DMAC_CTRLA_DST_WIDTH_HALF_WORD)
00097     #define I2S_WORD_BYTE_SIZE      2
00098 
00099 #elif  CONFIG_WORD_BIT_SIZE == 8
00100 
00101     #define I2S_TX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_BYTE | \
00102                                 DMAC_CTRLA_DST_WIDTH_BYTE)
00103     #define I2S_RX_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_BYTE | \
00104                                 DMAC_CTRLA_DST_WIDTH_BYTE)
00105     #define I2S_WORD_BYTE_SIZE      1
00106 
00107 #else
00108     #error Wrong i2s word size.
00109 #endif
00110 
00111
00112 #define I2S_STATUS_ERR              BV(0)
00113 #define I2S_STATUS_SINGLE_TRASF     BV(1)
00114 #define I2S_STATUS_TX               BV(2)
00115 #define I2S_STATUS_END_TX           BV(3)
00116 #define I2S_STATUS_RX               BV(4)
00117 #define I2S_STATUS_END_RX           BV(5)
00118 
00119
00120 static Event data_ready;
00121
00122 DmacDesc lli0;
00123 DmacDesc lli1;
00124 DmacDesc *curr;
00125 DmacDesc *next;
00126 DmacDesc *prev;
00127
00128 static uint8_t i2s_status;
00129 static uint8_t *sample_buff;
00130 static size_t next_idx = 0;
00131 static size_t chunk_size = 0;
00132 static size_t transfer_size = 0;
00133
00134 static void sam3_i2s_txStop(I2s *i2s)
00135 {
00136     (void)i2s;
00137     SSC_CR = BV(SSC_TXDIS);
00138     dmac_stop(I2S_DMAC_CH);
00139
00140     next_idx = 0;
00141     transfer_size = 0;
00142
00143     i2s_status |= I2S_STATUS_END_TX;
00144     i2s_status &= ~I2S_STATUS_TX;
00145     event_do(&data_ready);
00146 }
00147
00148 static void sam3_i2s_txWait(I2s *i2s)
00149 {
00150     (void)i2s;
00151     event_wait(&data_ready);
00152 }
00153
00154 static void i2s_dmac_irq(uint32_t status)
00155 {
00156     if (i2s_status & I2S_STATUS_SINGLE_TRASF)
00157     {
00158         i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
00159     }
00160     else
00161     {
00162         if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
00163         {
00164             i2s_status |= I2S_STATUS_ERR;
00165             // Disable to reset channel and clear fifo
00166             dmac_stop(I2S_DMAC_CH);
00167         }
00168         else
00169         {
00170             prev = curr;
00171             curr = next;
00172             next = prev;
00173
00174             if (i2s_status & I2S_STATUS_TX)
00175             {
00176                 curr->src_addr = (uint32_t)&sample_buff[next_idx];
00177                 curr->dst_addr = (uint32_t)&SSC_THR;
00178                 curr->dsc_addr = (uint32_t)next;
00179                 curr->ctrla    = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
00180                 curr->ctrlb    = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
00181             }
00182             else
00183             {
00184                 curr->src_addr = (uint32_t)&SSC_RHR;
00185                 curr->dst_addr = (uint32_t)&sample_buff[next_idx];
00186                 curr->dsc_addr = (uint32_t)next;
00187                 curr->ctrla    = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
00188                 curr->ctrlb    = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
00189             }
00190
00191         }
00192     }
00193     event_do(&data_ready);
00194 }
00195
00196
00197 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
00198 {
00199     ASSERT(buf);
00200     ASSERT(len >= slice_len);
00201     ASSERT(!(len % slice_len));
00202
00203     i2s_status &= ~(I2S_STATUS_END_TX | I2S_STATUS_SINGLE_TRASF);
00204
00205     sample_buff = (uint8_t *)buf;
00206     next_idx = 0;
00207     chunk_size = slice_len;
00208     size_t remaing_size = len;
00209     transfer_size = len;
00210
00211
00212     memset(&lli0, 0, sizeof(DmacDesc));
00213     memset(&lli1, 0, sizeof(DmacDesc));
00214
00215     prev = 0;
00216     curr = &lli1;
00217     next = &lli0;
00218
00219     for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
00220     {
00221         prev = curr;
00222         curr = next;
00223         next = prev;
00224
00225         i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
00226
00227         curr->src_addr = (uint32_t)&sample_buff[next_idx];
00228         curr->dst_addr = (uint32_t)&SSC_THR;
00229         curr->dsc_addr = (uint32_t)next;
00230         curr->ctrla    = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
00231         curr->ctrlb    = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
00232
00233         remaing_size -= chunk_size;
00234         next_idx += chunk_size;
00235
00236         if (remaing_size <= 0)
00237         {
00238             remaing_size = transfer_size;
00239             next_idx = 0;
00240         }
00241     }
00242
00243     dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG);
00244
00245     if (dmac_start(I2S_DMAC_CH) < 0)
00246     {
00247         LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
00248         return;
00249     }
00250
00251     i2s_status &= ~I2S_STATUS_ERR;
00252     i2s_status |= I2S_STATUS_TX;
00253
00254     SSC_CR = BV(SSC_TXEN);
00255
00256     while (1)
00257     {
00258         event_wait(&data_ready);
00259         I2S_STROBE_ON();
00260         remaing_size -= chunk_size;
00261         next_idx += chunk_size;
00262
00263         if (remaing_size <= 0)
00264         {
00265             remaing_size = transfer_size;
00266             next_idx = 0;
00267         }
00268
00269         if (i2s_status & I2S_STATUS_ERR)
00270         {
00271             LOG_ERR("Error while streaming.\n");
00272             break;
00273         }
00274
00275         if (i2s_status & I2S_STATUS_END_TX)
00276         {
00277             LOG_INFO("Stop streaming.\n");
00278             break;
00279         }
00280
00281         i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
00282         I2S_STROBE_OFF();
00283     }
00284 }
00285
00286 static void sam3_i2s_rxStop(I2s *i2s)
00287 {
00288     (void)i2s;
00289     SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS);
00290     dmac_stop(I2S_DMAC_CH);
00291
00292     i2s_status |= I2S_STATUS_END_RX;
00293     next_idx = 0;
00294     transfer_size = 0;
00295
00296     i2s_status &= ~I2S_STATUS_RX;
00297
00298     event_do(&data_ready);
00299 }
00300
00301 static void sam3_i2s_rxWait(I2s *i2s)
00302 {
00303     (void)i2s;
00304     event_wait(&data_ready);
00305 }
00306
00307 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
00308 {
00309     ASSERT(buf);
00310     ASSERT(len >= slice_len);
00311     ASSERT(!(len % slice_len));
00312
00313     i2s_status &= ~(I2S_STATUS_END_RX | I2S_STATUS_SINGLE_TRASF);
00314
00315     sample_buff = (uint8_t *)buf;
00316     next_idx = 0;
00317     chunk_size = slice_len;
00318     size_t remaing_size = len;
00319     transfer_size = len;
00320
00321     memset(&lli0, 0, sizeof(DmacDesc));
00322     memset(&lli1, 0, sizeof(DmacDesc));
00323
00324     prev = 0;
00325     curr = &lli1;
00326     next = &lli0;
00327
00328     for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
00329     {
00330         prev = curr;
00331         curr = next;
00332         next = prev;
00333
00334         curr->src_addr = (uint32_t)&SSC_RHR;
00335         curr->dst_addr = (uint32_t)&sample_buff[next_idx];
00336         curr->dsc_addr = (uint32_t)next;
00337         curr->ctrla    = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
00338         curr->ctrlb    = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
00339
00340         remaing_size -= chunk_size;
00341         next_idx += chunk_size;
00342
00343         if (remaing_size <= 0)
00344         {
00345             remaing_size = transfer_size;
00346             next_idx = 0;
00347         }
00348     }
00349
00350     dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
00351
00352     if (dmac_start(I2S_DMAC_CH) < 0)
00353     {
00354         LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
00355         return;
00356     }
00357
00358     i2s_status &= ~I2S_STATUS_ERR;
00359     i2s_status |= I2S_STATUS_RX;
00360
00361     SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
00362
00363     while (1)
00364     {
00365         event_wait(&data_ready);
00366         I2S_STROBE_ON();
00367         i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
00368
00369         remaing_size -= chunk_size;
00370         next_idx += chunk_size;
00371
00372         if (remaing_size <= 0)
00373         {
00374             remaing_size = transfer_size;
00375             next_idx = 0;
00376         }
00377
00378         if (i2s_status & I2S_STATUS_ERR)
00379         {
00380             LOG_ERR("Error while streaming.\n");
00381             break;
00382         }
00383
00384         if (i2s_status & I2S_STATUS_END_RX)
00385         {
00386             LOG_INFO("Stop streaming.\n");
00387             break;
00388         }
00389         I2S_STROBE_OFF();
00390     }
00391 }
00392
00393
00394 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
00395 {
00396     (void)i2s;
00397     return (i2s_status & I2S_STATUS_END_TX);
00398 }
00399
00400 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
00401 {
00402     (void)i2s;
00403     return (i2s_status & I2S_STATUS_END_RX);
00404 }
00405
00406 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
00407 {
00408     (void)i2s;
00409     i2s_status |= I2S_STATUS_SINGLE_TRASF;
00410
00411     dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
00412     dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB);
00413     dmac_start(I2S_DMAC_CH);
00414
00415     SSC_CR = BV(SSC_TXEN);
00416 }
00417
00418 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
00419 {
00420     (void)i2s;
00421
00422     i2s_status |= I2S_STATUS_SINGLE_TRASF;
00423
00424     dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
00425     dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB);
00426     dmac_start(I2S_DMAC_CH);
00427
00428     SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
00429 }
00430
00431 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
00432 {
00433     (void)i2s;
00434
00435     SSC_CR = BV(SSC_TXEN);
00436     while(!(SSC_SR & BV(SSC_TXRDY)))
00437         cpu_relax();
00438
00439     SSC_THR = sample;
00440     return 0;
00441 }
00442
00443 static uint32_t sam3_i2s_read(struct I2s *i2s)
00444 {
00445     (void)i2s;
00446
00447     SSC_CR = BV(SSC_RXEN);
00448     while(!(SSC_SR & BV(SSC_RXRDY)))
00449         cpu_relax();
00450
00451     return SSC_RHR;
00452 }
00453
00454
00455 /* We divite for 2 because the min clock for i2s i MCLK/2 */
00456 #define MCK_DIV     (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
00457 #define DATALEN     ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
00458 #define DELAY       ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
00459 #define PERIOD      ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
00460 #define DATNB       ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
00461 #define FSLEN       ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
00462 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
00463 
00464 void i2s_init(I2s *i2s, int channel)
00465 {
00466     (void)channel;
00467     i2s->ctx.write = sam3_i2s_write;
00468     i2s->ctx.tx_buf = sam3_i2s_txBuf;
00469     i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
00470     i2s->ctx.tx_start = sam3_i2s_txStart;
00471     i2s->ctx.tx_wait = sam3_i2s_txWait;
00472     i2s->ctx.tx_stop = sam3_i2s_txStop;
00473
00474     i2s->ctx.read = sam3_i2s_read;
00475     i2s->ctx.rx_buf = sam3_i2s_rxBuf;
00476     i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
00477     i2s->ctx.rx_start = sam3_i2s_rxStart;
00478     i2s->ctx.rx_wait = sam3_i2s_rxWait;
00479     i2s->ctx.rx_stop = sam3_i2s_rxStop;
00480
00481     DB(i2s->ctx._type = I2S_SAM3X;)
00482
00483     I2S_STROBE_INIT();
00484
00485     PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
00486     PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
00487
00488     PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
00489     PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
00490
00491     /* clock the ssc */
00492     pmc_periphEnable(SSC_ID);
00493
00494     /* reset device */
00495     SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
00496
00497     /* Set transmission clock */
00498     SSC_CMR = MCK_DIV & SSC_DIV_MASK;
00499     /* Set the transmission mode:
00500      * - the clk is generate from master clock
00501      * - clock only during transfer
00502      * - transmit Clock Gating Selection none
00503      * - DELAY cycle insert before starting transmission
00504      * - generate frame sync each 2*(PERIOD + 1) tramit clock
00505      * - Receive start on falling edge RF
00506      */
00507     SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
00508     /* Set the transmission frame mode:
00509      * - data len DATALEN + 1
00510      * - word per frame DATNB + 1
00511      * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
00512      * - DELAY cycle insert before starting transmission
00513      * - MSB
00514      * - Frame sync output selection negative
00515      */
00516     SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
00517
00518
00519     // Receiver should start on TX and take the clock from TK
00520     SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
00521     SSC_RFMR = DATALEN | DATNB | FSLEN  | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
00522
00523
00524     SSC_IDR = 0xFFFFFFFF;
00525
00526     dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
00527     event_initGeneric(&data_ready);
00528 }