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sam3.h
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00001 00036 #ifndef SAM3_H 00037 #define SAM3_H 00038 00039 #include <cpu/detect.h> 00040 #include <cfg/compiler.h> 00041 00042 /* 00043 * Peripherals IDs. 00044 */ 00045 /*\{*/ 00046 #if CPU_CM3_SAM3N 00047 #define SUPC_ID 0 ///< Supply Controller (SUPC) 00048 #define RSTC_ID 1 ///< Reset Controller (RSTC) 00049 #define RTC_ID 2 ///< Real Time Clock (RTC) 00050 #define RTT_ID 3 ///< Real Time Timer (RTT) 00051 #define WDT_ID 4 ///< Watchdog Timer (WDT) 00052 #define PMC_ID 5 ///< Power Management Controller (PMC) 00053 #define EEFC0_ID 6 ///< Enhanced Flash Controller 00054 #define UART0_ID 8 ///< UART 0 (UART0) 00055 #define UART1_ID 9 ///< UART 1 (UART1) 00056 #define PIOA_ID 11 ///< Parallel I/O Controller A (PIOA) 00057 #define PIOB_ID 12 ///< Parallel I/O Controller B (PIOB) 00058 #define PIOC_ID 13 ///< Parallel I/O Controller C (PIOC) 00059 #define US0_ID 14 ///< USART 0 (USART0) 00060 #define US1_ID 15 ///< USART 1 (USART1) 00061 #define TWI0_ID 19 ///< Two Wire Interface 0 (TWI0) 00062 #define TWI1_ID 20 ///< Two Wire Interface 1 (TWI1) 00063 #define SPI0_ID 21 ///< Serial Peripheral Interface (SPI) 00064 #define TC0_ID 23 ///< Timer/Counter 0 (TC0) 00065 #define TC1_ID 24 ///< Timer/Counter 1 (TC1) 00066 #define TC2_ID 25 ///< Timer/Counter 2 (TC2) 00067 #define TC3_ID 26 ///< Timer/Counter 3 (TC3) 00068 #define TC4_ID 27 ///< Timer/Counter 4 (TC4) 00069 #define TC5_ID 28 ///< Timer/Counter 5 (TC5) 00070 #define ADC_ID 29 ///< Analog To Digital Converter (ADC) 00071 #define DACC_ID 30 ///< Digital To Analog Converter (DACC) 00072 #define PWM_ID 31 ///< Pulse Width Modulation (PWM) 00073 #elif CPU_CM3_SAM3X 00074 #define SUPC_ID 0 ///< Supply Controller (SUPC) 00075 #define RSTC_ID 1 ///< Reset Controller (RSTC) 00076 #define RTC_ID 2 ///< Real Time Clock (RTC) 00077 #define RTT_ID 3 ///< Real Time Timer (RTT) 00078 #define WDT_ID 4 ///< Watchdog Timer (WDT) 00079 #define PMC_ID 5 ///< Power Management Controller (PMC) 00080 #define EEFC0_ID 6 ///< Enhanced Flash Controller 00081 #define EEFC1_ID 7 ///< Enhanced Flash Controller 00082 #define UART0_ID 8 ///< UART 0 (UART0) 00083 #define SMC_SDRAMC_ID 9 ///< Satic memory controller / SDRAM controller 00084 #define SDRAMC_ID 10 ///< Satic memory controller / SDRAM controller 00085 #define PIOA_ID 11 ///< Parallel I/O Controller A 00086 #define PIOB_ID 12 ///< Parallel I/O Controller B 00087 #define PIOC_ID 13 ///< Parallel I/O Controller C 00088 #define PIOD_ID 14 ///< Parallel I/O Controller D 00089 #define PIOE_ID 15 ///< Parallel I/O Controller E 00090 #define PIOF_ID 16 ///< Parallel I/O Controller F 00091 #define US0_ID 17 ///< USART 0 00092 #define US1_ID 18 ///< USART 1 00093 #define US2_ID 19 ///< USART 2 00094 #define US3_ID 20 ///< USART 3 00095 #define HSMCI_ID 21 ///< High speed multimedia card interface 00096 #define TWI0_ID 22 ///< Two Wire Interface 0 00097 #define TWI1_ID 23 ///< Two Wire Interface 1 00098 #define SPI0_ID 24 ///< Serial Peripheral Interface 00099 #define SPI1_ID 25 ///< Serial Peripheral Interface 00100 #define SSC_ID 26 ///< Synchronous serial controller 00101 #define TC0_ID 27 ///< Timer/Counter 0 00102 #define TC1_ID 28 ///< Timer/Counter 1 00103 #define TC2_ID 29 ///< Timer/Counter 2 00104 #define TC3_ID 30 ///< Timer/Counter 3 00105 #define TC4_ID 31 ///< Timer/Counter 4 00106 #define TC5_ID 32 ///< Timer/Counter 5 00107 #define TC6_ID 33 ///< Timer/Counter 6 00108 #define TC7_ID 34 ///< Timer/Counter 7 00109 #define TC8_ID 35 ///< Timer/Counter 8 00110 #define PWM_ID 36 ///< Pulse width modulation controller 00111 #define ADC_ID 37 ///< ADC controller 00112 #define DACC_ID 38 ///< DAC controller 00113 #define DMAC_ID 39 ///< DMA controller 00114 #define UOTGHS_ID 40 ///< USB OTG high speed 00115 #define TRNG_ID 41 ///< True random number generator 00116 #define EMAC_ID 42 ///< Ethernet MAC 00117 #define CAN0_ID 43 ///< CAN controller 0 00118 #define CAN1_ID 44 ///< CAN controller 1 00119 #else 00120 #error Peripheral IDs undefined 00121 #endif 00122 /*\}*/ 00123 00124 /* 00125 * Hardware features for drivers. 00126 */ 00127 #define USART_HAS_PDC 1 00128 #define SPI_HAS_PDC 1 00129 00130 #if CPU_CM3_SAM3X || CPU_CM3_SAM3U 00131 #define USART_PORTS 1 00132 #define UART_PORTS 4 00133 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S 00134 #define USART_PORTS 2 00135 #define UART_PORTS 2 00136 #else 00137 #error undefined U(S)ART_PORTS for this cpu 00138 #endif 00139 00140 #include "sam3_sysctl.h" 00141 #include "sam3_pdc.h" 00142 #include "sam3_pmc.h" 00143 #include "sam3_dmac.h" 00144 #include "sam3_smc.h" 00145 #include "sam3_sdramc.h" 00146 #include "sam3_ints.h" 00147 #include "sam3_pio.h" 00148 #include "sam3_nvic.h" 00149 #include "sam3_uart.h" 00150 #include "sam3_usart.h" 00151 #include "sam3_spi.h" 00152 #include "sam3_flash.h" 00153 #include "sam3_wdt.h" 00154 #include "sam3_emac.h" 00155 #include "sam3_rstc.h" 00156 #include "sam3_adc.h" 00157 #include "sam3_dacc.h" 00158 #include "sam3_tc.h" 00159 #include "sam3_twi.h" 00160 #include "sam3_ssc.h" 00161 #include "sam3_hsmci.h" 00162 #include "sam3_chipid.h" 00163 00167 /*\{*/ 00168 #if CPU_CM3_SAM3U 00169 #define UART0_PORT PIOA_BASE 00170 #define USART0_PORT PIOA_BASE 00171 #define USART1_PORT PIOA_BASE 00172 #define USART2_PORT PIOA_BASE 00173 #define USART3_PORT PIOC_BASE 00174 00175 #define UART0_PERIPH PIO_PERIPH_A 00176 #define USART0_PERIPH PIO_PERIPH_A 00177 #define USART1_PERIPH PIO_PERIPH_A 00178 #define USART2_PERIPH PIO_PERIPH_A 00179 #define USART3_PERIPH PIO_PERIPH_B 00180 00181 #define URXD0 11 00182 #define UTXD0 12 00183 #define RXD0 19 00184 #define TXD0 18 00185 #define RXD1 21 00186 #define TXD1 20 00187 #define RXD2 23 00188 #define TXD2 22 00189 #define RXD3 13 00190 #define TXD3 12 00191 #elif CPU_CM3_SAM3X 00192 #define UART0_PORT PIOA_BASE 00193 #define USART0_PORT PIOA_BASE 00194 #define USART1_PORT PIOA_BASE 00195 #define USART2_PORT PIOB_BASE 00196 #define USART3_PORT PIOD_BASE 00197 00198 #define UART0_PERIPH PIO_PERIPH_A 00199 #define USART0_PERIPH PIO_PERIPH_A 00200 #define USART1_PERIPH PIO_PERIPH_A 00201 #define USART2_PERIPH PIO_PERIPH_A 00202 #define USART3_PERIPH PIO_PERIPH_B 00203 00204 #define URXD0 8 00205 #define UTXD0 9 00206 #define RXD0 10 00207 #define TXD0 11 00208 #define RXD1 12 00209 #define TXD1 13 00210 #define RXD2 21 00211 #define TXD2 20 00212 #define RXD3 5 00213 #define TXD3 4 00214 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S 00215 #define UART0_PORT PIOA_BASE 00216 #define UART1_PORT PIOB_BASE 00217 #define USART0_PORT PIOA_BASE 00218 #define USART1_PORT PIOA_BASE 00219 00220 #define UART0_PERIPH PIO_PERIPH_A 00221 #define UART1_PERIPH PIO_PERIPH_A 00222 #define USART0_PERIPH PIO_PERIPH_A 00223 #define USART1_PERIPH PIO_PERIPH_A 00224 00225 #define URXD0 9 00226 #define UTXD0 10 00227 #define URXD1 2 00228 #define UTXD1 3 00229 #define RXD0 5 00230 #define TXD0 6 00231 #define RXD1 21 00232 #define TXD1 22 00233 #endif 00234 /*\}*/ 00235 00239 /*\{*/ 00240 #if CPU_CM3_SAM3U 00241 #define SPI0_SPCK 15 00242 #define SPI0_MOSI 14 00243 #define SPI0_MISO 13 00244 #elif CPU_CM3_SAM3X 00245 #define SPI0_SPCK 27 00246 #define SPI0_MOSI 26 00247 #define SPI0_MISO 25 00248 #else 00249 #define SPI0_SPCK 14 00250 #define SPI0_MOSI 13 00251 #define SPI0_MISO 12 00252 #endif 00253 /*\}*/ 00254 00258 /*\{*/ 00259 #if CPU_CM3_SAM3X 00260 #define TWI0_PORT PIOA_BASE 00261 #define TWI1_PORT PIOA_BASE 00262 00263 #define TWI0_PERIPH PIO_PERIPH_A 00264 #define TWI1_PERIPH PIO_PERIPH_A 00265 00266 #define TWI0_TWD 17 00267 #define TWI0_TWCK 18 00268 #define TWI1_TWD 12 00269 #define TWI1_TWCK 13 00270 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S 00271 #define TWI0_PORT PIOA_BASE 00272 #define TWI1_PORT PIOB_BASE 00273 00274 #define TWI0_PERIPH PIO_PERIPH_A 00275 #define TWI1_PERIPH PIO_PERIPH_A 00276 00277 #define TWI0_TWD 3 00278 #define TWI0_TWCK 4 00279 #define TWI1_TWD 4 00280 #define TWI1_TWCK 5 00281 #elif CPU_CM3_SAM3U 00282 #define TWI0_PORT PIOA_BASE 00283 #define TWI1_PORT PIOA_BASE 00284 00285 #define TWI0_PERIPH PIO_PERIPH_A 00286 #define TWI1_PERIPH PIO_PERIPH_A 00287 00288 #define TWI0_TWD 9 00289 #define TWI0_TWCK 10 00290 #define TWI1_TWD 24 00291 #define TWI1_TWCK 25 00292 #endif 00293 00294 #if CPU_CM3_SAM3X 00295 #define SSC_PORT PIOA_BASE 00296 #define SSC_PIO_PDR PIOA_PDR 00297 #define SSC_RECV_PERIPH PIO_PERIPH_A 00298 #define SSC_TRAN_PERIPH PIO_PERIPH_B 00299 #define SSC_RD 18 00300 #define SSC_RF 17 00301 #define SSC_RK 19 00302 #define SSC_TD 16 00303 #define SSC_TF 15 00304 #define SSC_TK 14 00305 #elif CPU_CM3_SAM3N 00306 #define SSC_PORT /* None! */ 00307 #define SSC_PIO_PDR /* None! */ 00308 #define SSC_RECV_PERIPH /* None! */ 00309 #define SSC_TRAN_PERIPH /* None! */ 00310 #define SSC_RD /* None! */ 00311 #define SSC_RF /* None! */ 00312 #define SSC_RK /* None! */ 00313 #define SSC_TD /* None! */ 00314 #define SSC_TF /* None! */ 00315 #define SSC_TK /* None! */ 00316 #elif CPU_CM3_SAM3S 00317 #define SSC_PORT PIOA_BASE 00318 #define SSC_PIO_PDR PIOA_PDR 00319 #define SSC_RECV_PERIPH PIO_PERIPH_A 00320 #define SSC_TRAN_PERIPH PIO_PERIPH_A 00321 #define SSC_RD 18 00322 #define SSC_RF 20 00323 #define SSC_RK 19 00324 #define SSC_TD 17 00325 #define SSC_TF 15 00326 #define SSC_TK 16 00327 #elif CPU_CM3_SAM3U 00328 #define SSC_PORT PIOA_BASE 00329 #define SSC_PIO_PDR PIOA_PDR 00330 #define SSC_RECV_PERIPH PIO_PERIPH_A 00331 #define SSC_TRAN_PERIPH PIO_PERIPH_A 00332 #define SSC_RD 27 00333 #define SSC_RF 31 00334 #define SSC_RK 29 00335 #define SSC_TD 26 00336 #define SSC_TF 30 00337 #define SSC_TK 28 00338 #else 00339 #error no ssc pins are defined for this cpu 00340 #endif 00341 00342 00343 #if CPU_CM3_SAM3X8 00344 #define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size 00345 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00346 #define FLASH_BANKS_NUM 2 ///< Number of flash banks 00347 #define FLASH_PAGES_FOR_BANK 1024 ///< Number pages for each bank 00348 #define FLASH_BASE 0x80000 ///< Start address for bank 0 00349 #elif CPU_CM3_SAM3U4 00350 #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size 00351 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00352 #define FLASH_BANKS_NUM 2 ///< Number of flash banks 00353 #define FLASH_PAGES_FOR_BANK 512 ///< Number pages for each bank 00354 #define FLASH_BASE 0x80000 ///< Start address for bank 0 00355 #elif CPU_CM3_SAM3N4 || CPU_CM3_SAM3S4 00356 #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size 00357 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes 00358 #define FLASH_BANKS_NUM 1 ///< Number of flash banks 00359 #define FLASH_PAGES_FOR_BANK 1024 ///< Number pages for each bank 00360 #define FLASH_BASE 0x400000 ///< Start address for bank 0 00361 #else 00362 #error no internal flash info are defined for this cpu 00363 #endif 00364 00365 00366 #if CPU_CM3_SAM3X8 00367 // Port B 00368 #define PHY_REFCLK_XT2_BIT 0 00369 #define PHY_TXEN_BIT 1 00370 #define PHY_TXD0_BIT 2 00371 #define PHY_TXD1_BIT 3 00372 #define PHY_RXDV_TESTMODE_BIT 4 00373 #define PHY_RXD0_AD0_BIT 5 00374 #define PHY_RXD1_AD1_BIT 6 00375 #define PHY_RXER_RXD4_RPTR_BIT 7 00376 #define PHY_MDC_BIT 8 00377 #define PHY_MDIO_BIT 9 00378 // Port A 00379 #define PHY_MDINTR_BIT 5 00380 #elif (CPU_CM3_SAM3U || CPU_CM3_SAM3N) 00381 /* No ethernet interface is present on this cpu */ 00382 #else 00383 #error No MII/RMII PHY pins interface was define for select CPU. 00384 #endif 00385 00386 #define PHY_MII_PINS_PORTB \ 00387 BV(PHY_REFCLK_XT2_BIT) \ 00388 | BV(PHY_TXEN_BIT) \ 00389 | BV(PHY_TXD0_BIT) \ 00390 | BV(PHY_TXD1_BIT) \ 00391 | BV(PHY_RXD0_AD0_BIT) \ 00392 | BV(PHY_RXD1_AD1_BIT) \ 00393 | BV(PHY_RXER_RXD4_RPTR_BIT) \ 00394 | BV(PHY_MDC_BIT) \ 00395 | BV(PHY_MDIO_BIT) 00396 00397 00398 #endif /* SAM3_H */
