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sam3_dmac.h
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00001 00038 #ifndef SAM3_DMAC_H 00039 #define SAM3_DMAC_H 00040 00042 #define DMAC_BASE 0x400C4000 00043 00044 #define DMAC_GCFG (*((reg32_t *)(DMAC_BASE + 0x000))) ///< Global Configuration Register. 00045 #define DMAC_EN (*((reg32_t *)(DMAC_BASE + 0x004))) ///< Enable Register. 00046 #define DMAC_SREQ (*((reg32_t *)(DMAC_BASE + 0x008))) ///< Software Single Request Register. 00047 #define DMAC_CREQ (*((reg32_t *)(DMAC_BASE + 0x00C))) ///< Software Chunk Transfer Request Register. 00048 #define DMAC_LAST (*((reg32_t *)(DMAC_BASE + 0x010))) ///< Software Last Transfer Flag Register. 00049 #define DMAC_EBCIER (*((reg32_t *)(DMAC_BASE + 0x018))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. 00050 #define DMAC_EBCIDR (*((reg32_t *)(DMAC_BASE + 0x01C))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. 00051 #define DMAC_EBCIMR (*((reg32_t *)(DMAC_BASE + 0x020))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. 00052 #define DMAC_EBCISR (*((reg32_t *)(DMAC_BASE + 0x024))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. 00053 #define DMAC_CHER (*((reg32_t *)(DMAC_BASE + 0x028))) ///< Channel Handler Enable Register. 00054 #define DMAC_CHDR (*((reg32_t *)(DMAC_BASE + 0x02C))) ///< Channel Handler Disable Register. 00055 #define DMAC_CHSR (*((reg32_t *)(DMAC_BASE + 0x030))) ///< Channel Handler Status Register. 00056 #define DMAC_SADDR0 (*((reg32_t *)(DMAC_BASE + 0x03C))) ///< Channel Source Address Register (ch_num = 0). 00057 #define DMAC_DADDR0 (*((reg32_t *)(DMAC_BASE + 0x040))) ///< Channel Destination Address Register (ch_num = 0). 00058 #define DMAC_DSCR0 (*((reg32_t *)(DMAC_BASE + 0x044))) ///< Channel Descriptor Address Register (ch_num = 0). 00059 #define DMAC_CTRLA0 (*((reg32_t *)(DMAC_BASE + 0x048))) ///< Channel Control A Register (ch_num = 0). 00060 #define DMAC_CTRLB0 (*((reg32_t *)(DMAC_BASE + 0x04C))) ///< Channel Control B Register (ch_num = 0). 00061 #define DMAC_CFG0 (*((reg32_t *)(DMAC_BASE + 0x050))) ///< Channel Configuration Register (ch_num = 0). 00062 #define DMAC_SADDR1 (*((reg32_t *)(DMAC_BASE + 0x064))) ///< Channel Source Address Register (ch_num = 1). 00063 #define DMAC_DADDR1 (*((reg32_t *)(DMAC_BASE + 0x068))) ///< Channel Destination Address Register (ch_num = 1). 00064 #define DMAC_DSCR1 (*((reg32_t *)(DMAC_BASE + 0x06C))) ///< Channel Descriptor Address Register (ch_num = 1). 00065 #define DMAC_CTRLA1 (*((reg32_t *)(DMAC_BASE + 0x070))) ///< Channel Control A Register (ch_num = 1). 00066 #define DMAC_CTRLB1 (*((reg32_t *)(DMAC_BASE + 0x074))) ///< Channel Control B Register (ch_num = 1). 00067 #define DMAC_CFG1 (*((reg32_t *)(DMAC_BASE + 0x078))) ///< Channel Configuration Register (ch_num = 1). 00068 #define DMAC_SADDR2 (*((reg32_t *)(DMAC_BASE + 0x08C))) ///< Channel Source Address Register (ch_num = 2). 00069 #define DMAC_DADDR2 (*((reg32_t *)(DMAC_BASE + 0x090))) ///< Channel Destination Address Register (ch_num = 2). 00070 #define DMAC_DSCR2 (*((reg32_t *)(DMAC_BASE + 0x094))) ///< Channel Descriptor Address Register (ch_num = 2). 00071 #define DMAC_CTRLA2 (*((reg32_t *)(DMAC_BASE + 0x098))) ///< Channel Control A Register (ch_num = 2). 00072 #define DMAC_CTRLB2 (*((reg32_t *)(DMAC_BASE + 0x09C))) ///< Channel Control B Register (ch_num = 2). 00073 #define DMAC_CFG2 (*((reg32_t *)(DMAC_BASE + 0x0A0))) ///< Channel Configuration Register (ch_num = 2). 00074 #define DMAC_SADDR3 (*((reg32_t *)(DMAC_BASE + 0x0B4))) ///< Channel Source Address Register (ch_num = 3). 00075 #define DMAC_DADDR3 (*((reg32_t *)(DMAC_BASE + 0x0B8))) ///< Channel Destination Address Register (ch_num = 3). 00076 #define DMAC_DSCR3 (*((reg32_t *)(DMAC_BASE + 0x0BC))) ///< Channel Descriptor Address Register (ch_num = 3). 00077 #define DMAC_CTRLA3 (*((reg32_t *)(DMAC_BASE + 0x0C0))) ///< Channel Control A Register (ch_num = 3). 00078 #define DMAC_CTRLB3 (*((reg32_t *)(DMAC_BASE + 0x0C4))) ///< Channel Control B Register (ch_num = 3). 00079 #define DMAC_CFG3 (*((reg32_t *)(DMAC_BASE + 0x0C8))) ///< Channel Configuration Register (ch_num = 3). 00080 #define DMAC_SADDR4 (*((reg32_t *)(DMAC_BASE + 0x0DC))) ///< Channel Source Address Register (ch_num = 4). 00081 #define DMAC_DADDR4 (*((reg32_t *)(DMAC_BASE + 0x0E0))) ///< Channel Destination Address Register (ch_num = 4). 00082 #define DMAC_DSCR4 (*((reg32_t *)(DMAC_BASE + 0x0E4))) ///< Channel Descriptor Address Register (ch_num = 4). 00083 #define DMAC_CTRLA4 (*((reg32_t *)(DMAC_BASE + 0x0E8))) ///< Channel Control A Register (ch_num = 4). 00084 #define DMAC_CTRLB4 (*((reg32_t *)(DMAC_BASE + 0x0EC))) ///< Channel Control B Register (ch_num = 4). 00085 #define DMAC_CFG4 (*((reg32_t *)(DMAC_BASE + 0x0F0))) ///< Channel Configuration Register (ch_num = 4). 00086 #define DMAC_SADDR5 (*((reg32_t *)(DMAC_BASE + 0x104))) ///< Channel Source Address Register (ch_num = 5). 00087 #define DMAC_DADDR5 (*((reg32_t *)(DMAC_BASE + 0x108))) ///< Channel Destination Address Register (ch_num = 5). 00088 #define DMAC_DSCR5 (*((reg32_t *)(DMAC_BASE + 0x10C))) ///< Channel Descriptor Address Register (ch_num = 5). 00089 #define DMAC_CTRLA5 (*((reg32_t *)(DMAC_BASE + 0x110))) ///< Channel Control A Register (ch_num = 5). 00090 #define DMAC_CTRLB5 (*((reg32_t *)(DMAC_BASE + 0x114))) ///< Channel Control B Register (ch_num = 5). 00091 #define DMAC_CFG5 (*((reg32_t *)(DMAC_BASE + 0x118))) ///< Channel Configuration Register (ch_num = 5). 00092 #define DMAC_WPMR (*((reg32_t *)(DMAC_BASE + 0x1E4))) ///< Write Protect Mode Register. 00093 #define DMAC_WPSR (*((reg32_t *)(DMAC_BASE + 0x1E8))) ///< Write Protect Status Register. 00094 00095 00096 00097 00098 /* 00099 * DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register 00100 */ 00101 #define DMAC_GCFG_ARB_CFG 4 ///< (DMAC_GCFG) Arbiter Configuration. 00102 00103 /* 00104 * DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register 00105 */ 00106 #define DMAC_EN_ENABLE 0 ///< (DMAC_EN). 00107 00108 /* 00109 * DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register 00110 */ 00111 #define DMAC_SREQ_SSREQ0 0 ///< (DMAC_SREQ) Source Request. 00112 #define DMAC_SREQ_DSREQ0 1 ///< (DMAC_SREQ) Destination Request. 00113 #define DMAC_SREQ_SSREQ1 2 ///< (DMAC_SREQ) Source Request. 00114 #define DMAC_SREQ_DSREQ1 3 ///< (DMAC_SREQ) Destination Request. 00115 #define DMAC_SREQ_SSREQ2 4 ///< (DMAC_SREQ) Source Request. 00116 #define DMAC_SREQ_DSREQ2 5 ///< (DMAC_SREQ) Destination Request. 00117 #define DMAC_SREQ_SSREQ3 6 ///< (DMAC_SREQ) Source Request. 00118 #define DMAC_SREQ_DSREQ3 7 ///< (DMAC_SREQ) Destination Request. 00119 #define DMAC_SREQ_SSREQ4 8 ///< (DMAC_SREQ) Source Request. 00120 #define DMAC_SREQ_DSREQ4 9 ///< (DMAC_SREQ) Destination Request. 00121 #define DMAC_SREQ_SSREQ5 10 ///< (DMAC_SREQ) Source Request. 00122 #define DMAC_SREQ_DSREQ5 11 ///< (DMAC_SREQ) Destination Request. 00123 00124 /* 00125 * DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register 00126 */ 00127 #define DMAC_CREQ_SCREQ0 0 ///< (DMAC_CREQ) Source Chunk Request. 00128 #define DMAC_CREQ_DCREQ0 1 ///< (DMAC_CREQ) Destination Chunk Request. 00129 #define DMAC_CREQ_SCREQ1 2 ///< (DMAC_CREQ) Source Chunk Request. 00130 #define DMAC_CREQ_DCREQ1 3 ///< (DMAC_CREQ) Destination Chunk Request. 00131 #define DMAC_CREQ_SCREQ2 4 ///< (DMAC_CREQ) Source Chunk Request. 00132 #define DMAC_CREQ_DCREQ2 5 ///< (DMAC_CREQ) Destination Chunk Request. 00133 #define DMAC_CREQ_SCREQ3 6 ///< (DMAC_CREQ) Source Chunk Request. 00134 #define DMAC_CREQ_DCREQ3 7 ///< (DMAC_CREQ) Destination Chunk Request. 00135 #define DMAC_CREQ_SCREQ4 8 ///< (DMAC_CREQ) Source Chunk Request. 00136 #define DMAC_CREQ_DCREQ4 9 ///< (DMAC_CREQ) Destination Chunk Request. 00137 #define DMAC_CREQ_SCREQ5 10 ///< (DMAC_CREQ) Source Chunk Request. 00138 #define DMAC_CREQ_DCREQ5 11 ///< (DMAC_CREQ) Destination Chunk Request. 00139 00140 /* 00141 * DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register 00142 */ 00143 #define DMAC_LAST_SLAST0 0 ///< (DMAC_LAST) Source Last. 00144 #define DMAC_LAST_DLAST0 1 ///< (DMAC_LAST) Destination Last. 00145 #define DMAC_LAST_SLAST1 2 ///< (DMAC_LAST) Source Last. 00146 #define DMAC_LAST_DLAST1 3 ///< (DMAC_LAST) Destination Last. 00147 #define DMAC_LAST_SLAST2 4 ///< (DMAC_LAST) Source Last. 00148 #define DMAC_LAST_DLAST2 5 ///< (DMAC_LAST) Destination Last. 00149 #define DMAC_LAST_SLAST3 6 ///< (DMAC_LAST) Source Last. 00150 #define DMAC_LAST_DLAST3 7 ///< (DMAC_LAST) Destination Last. 00151 #define DMAC_LAST_SLAST4 8 ///< (DMAC_LAST) Source Last. 00152 #define DMAC_LAST_DLAST4 9 ///< (DMAC_LAST) Destination Last. 00153 #define DMAC_LAST_SLAST5 10 ///< (DMAC_LAST) Source Last. 00154 #define DMAC_LAST_DLAST5 11 ///< (DMAC_LAST) Destination Last. 00155 00156 /* 00157 * DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, 00158 * Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. 00159 */ 00160 #define DMAC_EBCIER_BTC0 0 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00161 #define DMAC_EBCIER_BTC1 1 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00162 #define DMAC_EBCIER_BTC2 2 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00163 #define DMAC_EBCIER_BTC3 3 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00164 #define DMAC_EBCIER_BTC4 4 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00165 #define DMAC_EBCIER_BTC5 5 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0]. 00166 #define DMAC_EBCIER_CBTC0 8 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00167 #define DMAC_EBCIER_CBTC1 9 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00168 #define DMAC_EBCIER_CBTC2 10 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00169 #define DMAC_EBCIER_CBTC3 11 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00170 #define DMAC_EBCIER_CBTC4 12 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00171 #define DMAC_EBCIER_CBTC5 13 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0]. 00172 #define DMAC_EBCIER_ERR0 16 ///< (DMAC_EBCIER) Access Error [5:0]. 00173 #define DMAC_EBCIER_ERR1 17 ///< (DMAC_EBCIER) Access Error [5:0]. 00174 #define DMAC_EBCIER_ERR2 18 ///< (DMAC_EBCIER) Access Error [5:0]. 00175 #define DMAC_EBCIER_ERR3 19 ///< (DMAC_EBCIER) Access Error [5:0]. 00176 #define DMAC_EBCIER_ERR4 20 ///< (DMAC_EBCIER) Access Error [5:0]. 00177 #define DMAC_EBCIER_ERR5 21 ///< (DMAC_EBCIER) Access Error [5:0]. 00178 00179 /* DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.*/ 00180 #define DMAC_EBCIDR_BTC0 0 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00181 #define DMAC_EBCIDR_BTC1 1 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00182 #define DMAC_EBCIDR_BTC2 2 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00183 #define DMAC_EBCIDR_BTC3 3 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00184 #define DMAC_EBCIDR_BTC4 4 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00185 #define DMAC_EBCIDR_BTC5 5 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0]. 00186 #define DMAC_EBCIDR_CBTC0 8 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00187 #define DMAC_EBCIDR_CBTC1 9 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00188 #define DMAC_EBCIDR_CBTC2 10 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00189 #define DMAC_EBCIDR_CBTC3 11 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00190 #define DMAC_EBCIDR_CBTC4 12 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00191 #define DMAC_EBCIDR_CBTC5 13 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0]. 00192 #define DMAC_EBCIDR_ERR0 16 ///< (DMAC_EBCIDR) Access Error [5:0]. 00193 #define DMAC_EBCIDR_ERR1 17 ///< (DMAC_EBCIDR) Access Error [5:0]. 00194 #define DMAC_EBCIDR_ERR2 18 ///< (DMAC_EBCIDR) Access Error [5:0]. 00195 #define DMAC_EBCIDR_ERR3 19 ///< (DMAC_EBCIDR) Access Error [5:0]. 00196 #define DMAC_EBCIDR_ERR4 20 ///< (DMAC_EBCIDR) Access Error [5:0]. 00197 #define DMAC_EBCIDR_ERR5 21 ///< (DMAC_EBCIDR) Access Error [5:0]. 00198 00199 /* DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.*/ 00200 #define DMAC_EBCIMR_BTC0 0 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00201 #define DMAC_EBCIMR_BTC1 1 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00202 #define DMAC_EBCIMR_BTC2 2 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00203 #define DMAC_EBCIMR_BTC3 3 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00204 #define DMAC_EBCIMR_BTC4 4 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00205 #define DMAC_EBCIMR_BTC5 5 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0]. 00206 #define DMAC_EBCIMR_CBTC0 8 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00207 #define DMAC_EBCIMR_CBTC1 9 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00208 #define DMAC_EBCIMR_CBTC2 10 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00209 #define DMAC_EBCIMR_CBTC3 11 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00210 #define DMAC_EBCIMR_CBTC4 12 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00211 #define DMAC_EBCIMR_CBTC5 13 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0]. 00212 #define DMAC_EBCIMR_ERR0 16 ///< (DMAC_EBCIMR) Access Error [5:0]. 00213 #define DMAC_EBCIMR_ERR1 17 ///< (DMAC_EBCIMR) Access Error [5:0]. 00214 #define DMAC_EBCIMR_ERR2 18 ///< (DMAC_EBCIMR) Access Error [5:0]. 00215 #define DMAC_EBCIMR_ERR3 19 ///< (DMAC_EBCIMR) Access Error [5:0]. 00216 #define DMAC_EBCIMR_ERR4 20 ///< (DMAC_EBCIMR) Access Error [5:0]. 00217 #define DMAC_EBCIMR_ERR5 21 ///< (DMAC_EBCIMR) Access Error [5:0]. 00218 00219 /* DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.*/ 00220 #define DMAC_EBCISR_BTC0 0 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00221 #define DMAC_EBCISR_BTC1 1 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00222 #define DMAC_EBCISR_BTC2 2 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00223 #define DMAC_EBCISR_BTC3 3 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00224 #define DMAC_EBCISR_BTC4 4 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00225 #define DMAC_EBCISR_BTC5 5 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0]. 00226 #define DMAC_EBCISR_CBTC0 8 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00227 #define DMAC_EBCISR_CBTC1 9 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00228 #define DMAC_EBCISR_CBTC2 10 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00229 #define DMAC_EBCISR_CBTC3 11 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00230 #define DMAC_EBCISR_CBTC4 12 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00231 #define DMAC_EBCISR_CBTC5 13 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0]. 00232 #define DMAC_EBCISR_ERR0 16 ///< (DMAC_EBCISR) Access Error [5:0]. 00233 #define DMAC_EBCISR_ERR1 17 ///< (DMAC_EBCISR) Access Error [5:0]. 00234 #define DMAC_EBCISR_ERR2 18 ///< (DMAC_EBCISR) Access Error [5:0]. 00235 #define DMAC_EBCISR_ERR3 19 ///< (DMAC_EBCISR) Access Error [5:0]. 00236 #define DMAC_EBCISR_ERR4 20 ///< (DMAC_EBCISR) Access Error [5:0]. 00237 #define DMAC_EBCISR_ERR5 21 ///< (DMAC_EBCISR) Access Error [5:0]. 00238 00239 /* DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register*/ 00240 #define DMAC_CHER_ENA0 0 ///< (DMAC_CHER) Enable [5:0]. 00241 #define DMAC_CHER_ENA1 1 ///< (DMAC_CHER) Enable [5:0]. 00242 #define DMAC_CHER_ENA2 2 ///< (DMAC_CHER) Enable [5:0]. 00243 #define DMAC_CHER_ENA3 3 ///< (DMAC_CHER) Enable [5:0]. 00244 #define DMAC_CHER_ENA4 4 ///< (DMAC_CHER) Enable [5:0]. 00245 #define DMAC_CHER_ENA5 5 ///< (DMAC_CHER) Enable [5:0]. 00246 #define DMAC_CHER_SUSP0 8 ///< (DMAC_CHER) Suspend [5:0]. 00247 #define DMAC_CHER_SUSP1 9 ///< (DMAC_CHER) Suspend [5:0]. 00248 #define DMAC_CHER_SUSP2 10 ///< (DMAC_CHER) Suspend [5:0]. 00249 #define DMAC_CHER_SUSP3 11 ///< (DMAC_CHER) Suspend [5:0]. 00250 #define DMAC_CHER_SUSP4 12 ///< (DMAC_CHER) Suspend [5:0]. 00251 #define DMAC_CHER_SUSP5 13 ///< (DMAC_CHER) Suspend [5:0]. 00252 #define DMAC_CHER_KEEP0 24 ///< (DMAC_CHER) Keep on [5:0]. 00253 #define DMAC_CHER_KEEP1 25 ///< (DMAC_CHER) Keep on [5:0]. 00254 #define DMAC_CHER_KEEP2 26 ///< (DMAC_CHER) Keep on [5:0]. 00255 #define DMAC_CHER_KEEP3 27 ///< (DMAC_CHER) Keep on [5:0]. 00256 #define DMAC_CHER_KEEP4 28 ///< (DMAC_CHER) Keep on [5:0]. 00257 #define DMAC_CHER_KEEP5 29 ///< (DMAC_CHER) Keep on [5:0]. 00258 00259 /* DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register*/ 00260 #define DMAC_CHDR_DIS0 0 ///< (DMAC_CHDR) Disable [5:0]. 00261 #define DMAC_CHDR_DIS1 1 ///< (DMAC_CHDR) Disable [5:0]. 00262 #define DMAC_CHDR_DIS2 2 ///< (DMAC_CHDR) Disable [5:0]. 00263 #define DMAC_CHDR_DIS3 3 ///< (DMAC_CHDR) Disable [5:0]. 00264 #define DMAC_CHDR_DIS4 4 ///< (DMAC_CHDR) Disable [5:0]. 00265 #define DMAC_CHDR_DIS5 5 ///< (DMAC_CHDR) Disable [5:0]. 00266 #define DMAC_CHDR_RES0 8 ///< (DMAC_CHDR) Resume [5:0]. 00267 #define DMAC_CHDR_RES1 9 ///< (DMAC_CHDR) Resume [5:0]. 00268 #define DMAC_CHDR_RES2 10 ///< (DMAC_CHDR) Resume [5:0]. 00269 #define DMAC_CHDR_RES3 11 ///< (DMAC_CHDR) Resume [5:0]. 00270 #define DMAC_CHDR_RES4 12 ///< (DMAC_CHDR) Resume [5:0]. 00271 #define DMAC_CHDR_RES5 13 ///< (DMAC_CHDR) Resume [5:0]. 00272 00273 /* DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register*/ 00274 #define DMAC_CHSR_EN_MASK 0x31 ///< 00275 #define DMAC_CHSR_ENA0 0 ///< (DMAC_CHSR) Enable [5:0]. 00276 #define DMAC_CHSR_ENA1 1 ///< (DMAC_CHSR) Enable [5:0]. 00277 #define DMAC_CHSR_ENA2 2 ///< (DMAC_CHSR) Enable [5:0]. 00278 #define DMAC_CHSR_ENA3 3 ///< (DMAC_CHSR) Enable [5:0]. 00279 #define DMAC_CHSR_ENA4 4 ///< (DMAC_CHSR) Enable [5:0]. 00280 #define DMAC_CHSR_ENA5 5 ///< (DMAC_CHSR) Enable [5:0]. 00281 #define DMAC_CHSR_SUSP0 8 ///< (DMAC_CHSR) Suspend [5:0]. 00282 #define DMAC_CHSR_SUSP1 9 ///< (DMAC_CHSR) Suspend [5:0]. 00283 #define DMAC_CHSR_SUSP2 10 ///< (DMAC_CHSR) Suspend [5:0]. 00284 #define DMAC_CHSR_SUSP3 11 ///< (DMAC_CHSR) Suspend [5:0]. 00285 #define DMAC_CHSR_SUSP4 12 ///< (DMAC_CHSR) Suspend [5:0]. 00286 #define DMAC_CHSR_SUSP5 13 ///< (DMAC_CHSR) Suspend [5:0]. 00287 #define DMAC_CHSR_EMPT0 16 ///< (DMAC_CHSR) Empty [5:0]. 00288 #define DMAC_CHSR_EMPT1 17 ///< (DMAC_CHSR) Empty [5:0]. 00289 #define DMAC_CHSR_EMPT2 18 ///< (DMAC_CHSR) Empty [5:0]. 00290 #define DMAC_CHSR_EMPT3 19 ///< (DMAC_CHSR) Empty [5:0]. 00291 #define DMAC_CHSR_EMPT4 20 ///< (DMAC_CHSR) Empty [5:0]. 00292 #define DMAC_CHSR_EMPT5 21 ///< (DMAC_CHSR) Empty [5:0]. 00293 #define DMAC_CHSR_STAL0 24 ///< (DMAC_CHSR) Stalled [5:0]. 00294 #define DMAC_CHSR_STAL1 25 ///< (DMAC_CHSR) Stalled [5:0]. 00295 #define DMAC_CHSR_STAL2 26 ///< (DMAC_CHSR) Stalled [5:0]. 00296 #define DMAC_CHSR_STAL3 27 ///< (DMAC_CHSR) Stalled [5:0]. 00297 #define DMAC_CHSR_STAL4 28 ///< (DMAC_CHSR) Stalled [5:0]. 00298 #define DMAC_CHSR_STAL5 29 ///< (DMAC_CHSR) Stalled [5:0]. 00299 00300 /* DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register*/ 00301 #define DMAC_CTRLA_BTSIZE_MASK 0xffff ///< (DMAC_CTRLA) Buffer Transfer Size. 00302 #define DMAC_CTRLA_SCSIZE_MASK 0x70000 ///< (DMAC_CTRLA) Source Chunk Transfer Size.. 00303 #define DMAC_CTRLA_SCSIZE_CHK_1 0x00000 ///< (DMAC_CTRLA) 1 data transferred. 00304 #define DMAC_CTRLA_SCSIZE_CHK_4 0x10000 ///< (DMAC_CTRLA) 4 data transferred. 00305 #define DMAC_CTRLA_SCSIZE_CHK_8 0x20000 ///< (DMAC_CTRLA) 8 data transferred. 00306 #define DMAC_CTRLA_SCSIZE_CHK_16 0x30000 ///< (DMAC_CTRLA) 16 data transferred. 00307 #define DMAC_CTRLA_SCSIZE_CHK_32 0x40000 ///< (DMAC_CTRLA) 32 data transferred. 00308 #define DMAC_CTRLA_SCSIZE_CHK_64 0x50000 ///< (DMAC_CTRLA) 64 data transferred. 00309 #define DMAC_CTRLA_SCSIZE_CHK_128 0x60000 ///< (DMAC_CTRLA) 128 data transferred. 00310 #define DMAC_CTRLA_SCSIZE_CHK_256 0x70000 ///< (DMAC_CTRLA) 256 data transferred. 00311 #define DMAC_CTRLA_DCSIZE_MASK 0x700000 ///< (DMAC_CTRLA) Destination Chunk Transfer Size. 00312 #define DMAC_CTRLA_DCSIZE_CHK_1 0x000000 ///< (DMAC_CTRLA) 1 data transferred. 00313 #define DMAC_CTRLA_DCSIZE_CHK_4 0x100000 ///< (DMAC_CTRLA) 4 data transferred. 00314 #define DMAC_CTRLA_DCSIZE_CHK_8 0x200000 ///< (DMAC_CTRLA) 8 data transferred. 00315 #define DMAC_CTRLA_DCSIZE_CHK_16 0x300000 ///< (DMAC_CTRLA) 16 data transferred. 00316 #define DMAC_CTRLA_DCSIZE_CHK_32 0x400000 ///< (DMAC_CTRLA) 32 data transferred. 00317 #define DMAC_CTRLA_DCSIZE_CHK_64 0x500000 ///< (DMAC_CTRLA) 64 data transferred. 00318 #define DMAC_CTRLA_DCSIZE_CHK_128 0x600000 ///< (DMAC_CTRLA) 128 data transferred. 00319 #define DMAC_CTRLA_DCSIZE_CHK_256 0x700000 ///< (DMAC_CTRLA) 256 data transferred. 00320 #define DMAC_CTRLA_SRC_WIDTH_MASK 0x3000000 ///< (DMAC_CTRLA) Transfer Width for the Source. 00321 #define DMAC_CTRLA_SRC_WIDTH_BYTE 0x0000000 ///< (DMAC_CTRLA) the transfer size is set to 8-bit width. 00322 #define DMAC_CTRLA_SRC_WIDTH_HALF_WORD 0x1000000///< (DMAC_CTRLA) the transfer size is set to 16-bit width. 00323 #define DMAC_CTRLA_SRC_WIDTH_WORD 0x2000000 ///< (DMAC_CTRLA) the transfer size is set to 32-bit width. 00324 #define DMAC_CTRLA_DST_WIDTH_MASK 0x30000000 ///< (DMAC_CTRLA) Transfer Width for the Destination. 00325 #define DMAC_CTRLA_DST_WIDTH_BYTE 0x00000000 ///< (DMAC_CTRLA) the transfer size is set to 8-bit width. 00326 #define DMAC_CTRLA_DST_WIDTH_HALF_WORD 0x10000000///< (DMAC_CTRLA) the transfer size is set to 16-bit width. 00327 #define DMAC_CTRLA_DST_WIDTH_WORD 0x20000000 ///< (DMAC_CTRLA) the transfer size is set to 32-bit width. 00328 #define DMAC_CTRLA_DONE 31 ///< (DMAC_CTRLA) . 00329 00330 /* DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register*/ 00331 #define DMAC_CTRLB_SRC_DSCR 16 ///< (DMAC_CTRLB) Source Address Descriptor. 00332 #define DMAC_CTRLB_DST_DSCR 20 ///< (DMAC_CTRLB) Destination Address Descriptor. 00333 #define DMAC_CTRLB_FC_MASK 0xE00000 ///< (DMAC_CTRLB) Flow Control. 00334 #define DMAC_CTRLB_FC_MEM2MEM_DMA_FC 0 ///< (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller. 00335 #define DMAC_CTRLB_FC_MEM2PER_DMA_FC 0x200000 ///< (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller. 00336 #define DMAC_CTRLB_FC_PER2MEM_DMA_FC 0x400000 ///< (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller. 00337 #define DMAC_CTRLB_FC_PER2PER_DMA_FC 0x600000 ///< (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller. 00338 #define DMAC_CTRLB_SRC_INCR_MASK 0x3000000 ///< (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source. 00339 #define DMAC_CTRLB_SRC_INCR_INCREMENTING 0 ///< (DMAC_CTRLB) The source address is incremented. 00340 #define DMAC_CTRLB_SRC_INCR_DECREMENTING 0x1000000 ///< (DMAC_CTRLB) The source address is decremented. 00341 #define DMAC_CTRLB_SRC_INCR_FIXED 0x2000000 ///< (DMAC_CTRLB) The source address remains unchanged. 00342 #define DMAC_CTRLB_DST_INCR_MASK 0x30000000 ///< (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination. 00343 #define DMAC_CTRLB_DST_INCR_INCREMENTING 0 ///< (DMAC_CTRLB) The destination address is incremented. 00344 #define DMAC_CTRLB_DST_INCR_DECREMENTING 0x10000000 ///< (DMAC_CTRLB) The destination address is decremented. 00345 #define DMAC_CTRLB_DST_INCR_FIXED 0x20000000 ///< (DMAC_CTRLB) The destination address remains unchanged. 00346 #define DMAC_CTRLB_IEN 30 ///< (DMAC_CTRLB). 00347 00348 /* DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register*/ 00349 #define DMAC_CFG_SRC_PER_MASK 0xf ///< (DMAC_CFG) Source with Peripheral identifier. 00350 #define DMAC_CFG_DST_PER_MASK 0xf0 ///< (DMAC_CFG) Destination with Peripheral identifier. 00351 #define DMAC_CFG_DST_PER_SHIFT 4 ///< (DMAC_CFG) Destination with Peripheral identifier. 00352 #define DMAC_CFG_SRC_H2SEL 9 ///< (DMAC_CFG) Software or Hardware Selection for the Source. 00353 #define DMAC_CFG_DST_H2SEL 13 ///< (DMAC_CFG) Software or Hardware Selection for the Destination. 00354 #define DMAC_CFG_SOD 16 ///< (DMAC_CFG) Stop On Done. 00355 #define DMAC_CFG_LOCK_IF 20 ///< (DMAC_CFG) Interface Lock. 00356 #define DMAC_CFG_LOCK_B 21 ///< (DMAC_CFG) Bus Lock. 00357 #define DMAC_CFG_LOCK_IF_L 22 ///< (DMAC_CFG) Master Interface Arbiter Lock. 00358 #define DMAC_CFG_AHB_PROT_SHIFT 24 ///< (DMAC_CFG) AHB Protection. 00359 #define DMAC_CFG_AHB_PROT_MASK 0x7000000 ///< (DMAC_CFG) AHB Protection. 00360 #define DMAC_CFG_FIFOCFG_MASK 0x70000000 ///< (DMAC_CFG) FIFO Configuration. 00361 #define DMAC_CFG_FIFOCFG_ALAP_CFG 0x00000000 ///< (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface.. 00362 #define DMAC_CFG_FIFOCFG_HALF_CFG 0x10000000 ///< (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced.. 00363 #define DMAC_CFG_FIFOCFG_ASAP_CFG 0x20000000 ///< (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced.. 00364 /* DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register*/ 00365 #define DMAC_WPMR_WPEN 0 ///< (DMAC_WPMR) Write Protect Enable. 00366 #define DMAC_WPMR_WPKEY_MASK 0xFFFFFF00 ///< (DMAC_WPMR) Write Protect KEY. 00367 00368 /* DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register*/ 00369 #define DMAC_WPSR_WPVS 0 ///< (DMAC_WPSR) Write Protect Violation Status. 00370 #define DMAC_WPSR_WPVSRC_MASK 0x00FFFF00 ///< (DMAC_WPSR) Write Protect Violation Source. 00371 00372 00373 #endif /* SAM3_DMAC_H */ 00374
