Atmel SAM3 enhanced embedded flash controller definitions. More...
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Defines | |
| #define | EEFC0_BASE 0x400E0A00 |
| EEFC base registers addresses. | |
| #define | EEFC_FMR_OFF 0x0 |
| EFC register offsets. | |
| #define | EEFC_FCR_OFF 0x4 |
| Flash Command Register. | |
| #define | EEFC_FSR_OFF 0x8 |
| Flash Status Register. | |
| #define | EEFC_FRR_OFF 0xC |
| Flash Result Register. | |
| #define | EEFC0_FMR (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF))) |
| EEFC registers. | |
| #define | EEFC0_FCR (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF))) |
| Flash Command Register. | |
| #define | EEFC0_FSR (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF))) |
| Flash Status Register. | |
| #define | EEFC0_FRR (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF))) |
| Flash Result Register. | |
| #define | EEFC_FMR_FRDY 0 |
| Defines for bit fields in EEFC_FMR register. | |
| #define | EEFC_FMR_FWS_SHIFT 8 |
| Defines for bit fields in EEFC_FMR register. | |
| #define | EEFC_FMR_FWS_MASK (0xf << EEFC_FMR_FWS_SHIFT) |
| Flash Wait State. | |
| #define | EEFC_FMR_FWS(value) (EEFC_FMR_FWS_MASK & ((value) << EEFC_FMR_FWS_SHIFT)) |
| Defines for bit fields in EEFC_FMR register. | |
| #define | EEFC_FMR_FAM 24 |
| Flash Access Mode. | |
| #define | EFC_FCR_FCMD_MASK 0x000000FF |
| Defines for bit fields in EEFC_FCR register. | |
| #define | EFC_FCR_FCMD_GETD 0x00000000 |
| Get flash Descriptor. | |
| #define | EFC_FCR_FCMD_WP 0x00000001 |
| Write page. | |
| #define | EFC_FCR_FCMD_WPL 0x00000002 |
| Write page and lock. | |
| #define | EFC_FCR_FCMD_EWP 0x00000003 |
| Erase page and write page. | |
| #define | EFC_FCR_FCMD_EWPL 0x00000004 |
| Erase page and write page then lock. | |
| #define | EFC_FCR_FCMD_EA 0x00000005 |
| Erase all. | |
| #define | EFC_FCR_FCMD_SLB 0x00000008 |
| Set lock bit. | |
| #define | EFC_FCR_FCMD_CLB 0x00000009 |
| Clear lock bit. | |
| #define | EFC_FCR_FCMD_GLB 0x0000000A |
| Get lock bit. | |
| #define | EFC_FCR_FCMD_SGPB 0x0000000B |
| Set GPNVM bit. | |
| #define | EFC_FCR_FCMD_CGPB 0x0000000C |
| Clear GPNVM bit. | |
| #define | EFC_FCR_FCMD_GGPB 0x0000000D |
| Get GPNVM bit. | |
| #define | EFC_FCR_FCMD_STUI 0x0000000E |
| Start read uniqune identifier. | |
| #define | EFC_FCR_FCMD_SPUI 0x0000000F |
| Stop read uniqune identifier. | |
| #define | EFC_FCR_FCMD_GCALB 0x00000010 |
| Get CALIB bit. | |
| #define | EEFC_FCR_FARG_SHIFT 8 |
| Defines for bit fields in EEFC_FCR register. | |
| #define | EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) |
| Flash Command Argument. | |
| #define | EEFC_FCR_FARG(value) (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT)) |
| Defines for bit fields in EEFC_FCR register. | |
| #define | EEFC_FCR_FKEY 0x5A000000 |
| Writing protect key. | |
| #define | EEFC_FSR_FRDY 0 |
| Defines for bit fields in EEFC_FSR register. | |
| #define | EEFC_FSR_FCMDE 1 |
| Flash Command Error Status. | |
| #define | EEFC_FSR_FLOCKE 2 |
| Flash Lock Error Status. | |
Detailed Description
Atmel SAM3 enhanced embedded flash controller definitions.
Definition in file sam3_flash.h.
Define Documentation
| #define EEFC0_FMR (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF))) |
| #define EEFC_FCR_FARG | ( | value | ) | (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT)) |
Defines for bit fields in EEFC_FCR register.
Flash command mask.
Definition at line 112 of file sam3_flash.h.
| #define EEFC_FCR_FARG_SHIFT 8 |
Defines for bit fields in EEFC_FCR register.
Flash command mask.
Definition at line 110 of file sam3_flash.h.
| #define EEFC_FMR_FRDY 0 |
Defines for bit fields in EEFC_FMR register.
Ready Interrupt Enable
Definition at line 83 of file sam3_flash.h.
| #define EEFC_FMR_FWS | ( | value | ) | (EEFC_FMR_FWS_MASK & ((value) << EEFC_FMR_FWS_SHIFT)) |
Defines for bit fields in EEFC_FMR register.
Ready Interrupt Enable
Definition at line 86 of file sam3_flash.h.
| #define EEFC_FMR_FWS_SHIFT 8 |
Defines for bit fields in EEFC_FMR register.
Ready Interrupt Enable
Definition at line 84 of file sam3_flash.h.
| #define EEFC_FMR_OFF 0x0 |
| #define EEFC_FSR_FRDY 0 |
Defines for bit fields in EEFC_FSR register.
Flash Ready Status
Definition at line 120 of file sam3_flash.h.
| #define EFC_FCR_FCMD_MASK 0x000000FF |
Defines for bit fields in EEFC_FCR register.
Flash command mask.
Definition at line 94 of file sam3_flash.h.
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