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sam3_hsmci.h
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00001 00038 #ifndef SAM3_HSMCI_H 00039 #define SAM3_HSMCI_H 00040 00041 #include <cfg/compiler.h> 00042 00043 00044 #define HSMCI_BASE 0x40000000U 00045 00046 00047 #define HSMCI_CR (*((reg32_t *)(HSMCI_BASE + 0x000))) ///< (Hsmci Offset: 0x00) Control Register 00048 #define HSMCI_MR (*((reg32_t *)(HSMCI_BASE + 0x004))) ///< (Hsmci Offset: 0x04) Mode Register 00049 #define HSMCI_DTOR (*((reg32_t *)(HSMCI_BASE + 0x008))) ///< (Hsmci Offset: 0x08) Data Timeout Register 00050 #define HSMCI_SDCR (*((reg32_t *)(HSMCI_BASE + 0x00C))) ///< (Hsmci Offset: 0x0C) SD/SDIO Card Register 00051 #define HSMCI_ARGR (*((reg32_t *)(HSMCI_BASE + 0x010))) ///< (Hsmci Offset: 0x10) Argument Register 00052 #define HSMCI_CMDR (*((reg32_t *)(HSMCI_BASE + 0x014))) ///< (Hsmci Offset: 0x14) Command Register 00053 #define HSMCI_BLKR (*((reg32_t *)(HSMCI_BASE + 0x018))) ///< (Hsmci Offset: 0x18) Block Register 00054 #define HSMCI_CSTOR (*((reg32_t *)(HSMCI_BASE + 0x01C))) ///< (Hsmci Offset: 0x1C) Completion Signal Timeout Register 00055 #define HSMCI_RSPR (*((reg32_t *)(HSMCI_BASE + 0x020))) ///< (Hsmci Offset: 0x20) Response Register 00056 #define HSMCI_RSPR1 (*((reg32_t *)(HSMCI_BASE + 0x024))) ///< (Hsmci Offset: 0x24) Response Register 00057 #define HSMCI_RSPR2 (*((reg32_t *)(HSMCI_BASE + 0x028))) ///< (Hsmci Offset: 0x28) Response Register 00058 #define HSMCI_RSPR3 (*((reg32_t *)(HSMCI_BASE + 0x02C))) ///< (Hsmci Offset: 0x2C) Response Register 00059 #define HSMCI_RDR (*((reg32_t *)(HSMCI_BASE + 0x030))) ///< (Hsmci Offset: 0x30) Receive Data Register 00060 #define HSMCI_TDR (*((reg32_t *)(HSMCI_BASE + 0x034))) ///< (Hsmci Offset: 0x34) Transmit Data Register 00061 #define HSMCI_SR (*((reg32_t *)(HSMCI_BASE + 0x040))) ///< (Hsmci Offset: 0x40) Status Register 00062 #define HSMCI_IER (*((reg32_t *)(HSMCI_BASE + 0x044))) ///< (Hsmci Offset: 0x44) Interrupt Enable Register 00063 #define HSMCI_IDR (*((reg32_t *)(HSMCI_BASE + 0x048))) ///< (Hsmci Offset: 0x48) Interrupt Disable Register 00064 #define HSMCI_IMR (*((reg32_t *)(HSMCI_BASE + 0x04C))) ///< (Hsmci Offset: 0x4C) Interrupt Mask Register 00065 #define HSMCI_DMA (*((reg32_t *)(HSMCI_BASE + 0x050))) ///< (Hsmci Offset: 0x50) DMA Configuration Register 00066 #define HSMCI_CFG (*((reg32_t *)(HSMCI_BASE + 0x054))) ///< (Hsmci Offset: 0x54) Configuration Register 00067 #define HSMCI_WPMR (*((reg32_t *)(HSMCI_BASE + 0x0E4))) ///< (Hsmci Offset: 0xE4) Write Protection Mode Register 00068 #define HSMCI_WPSR (*((reg32_t *)(HSMCI_BASE + 0x0E8))) ///< (Hsmci Offset: 0xE8) Write Protection Status Register 00069 #define HSMCI_FIFO (*((reg32_t *)(HSMCI_BASE + 0x200))) ///< (Hsmci Offset: 0x200) FIFO Memory Aperture0 00070 00071 00072 /* HSMCI_CR : (HSMCI Offset: 0x00) Control Register */ 00073 #define HSMCI_CR_MCIEN 0 ///< (HSMCI_CR) Multi-Media Interface Enable. 00074 #define HSMCI_CR_MCIDIS 1 ///< (HSMCI_CR) Multi-Media Interface Disable. 00075 #define HSMCI_CR_PWSEN 2 ///< (HSMCI_CR) Power Save Mode Enable. 00076 #define HSMCI_CR_PWSDIS 3 ///< (HSMCI_CR) Power Save Mode Disable. 00077 #define HSMCI_CR_SWRST 7 ///< (HSMCI_CR) Software Reset. 00078 00079 /* HSMCI_MR : (HSMCI Offset: 0x04) Mode Register */ 00080 #define HSMCI_MR_CLKDIV_MASK 0xff ///< (HSMCI_MR) Clock Divider 00081 #define HSMCI_MR_PWSDIV_SHIFT 8 ///< (HSMCI_MR) Power Saving Divider 00082 #define HSMCI_MR_PWSDIV_MASK (0x7u << HSMCI_MR_PWSDIV_SHIFT) ///< (HSMCI_MR) Power Saving Divider 00083 #define HSMCI_MR_RDPROOF 11 ///< (HSMCI_MR) 00084 #define HSMCI_MR_WRPROOF 12 ///< (HSMCI_MR) 00085 #define HSMCI_MR_FBYTE 13 ///< (HSMCI_MR) Force Byte Transfer 00086 #define HSMCI_MR_PADV 14 ///< (HSMCI_MR) Padding Value 00087 #define HSMCI_MR_BLKLEN_SHIFT 16 00088 #define HSMCI_MR_BLKLEN_MASK (0xffffu << HSMCI_MR_BLKLEN_SHIFT) ///< (HSMCI_MR) Data Block Length 00089 00090 00091 /* HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register */ 00092 #define HSMCI_DTOR_DTOCYC_MASK 0xfu ///< (HSMCI_DTOR) Data Timeout Cycle Number 00093 #define HSMCI_DTOR_DTOMUL_SHIFT 4 00094 #define HSMCI_DTOR_DTOMUL_MASK (0x7u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) Data Timeout Multiplier 00095 #define HSMCI_DTOR_DTOMUL_1 (0x0u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC 00096 #define HSMCI_DTOR_DTOMUL_16 (0x1u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 16 00097 #define HSMCI_DTOR_DTOMUL_128 (0x2u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 128 00098 #define HSMCI_DTOR_DTOMUL_256 (0x3u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 256 00099 #define HSMCI_DTOR_DTOMUL_1024 (0x4u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 1024 00100 #define HSMCI_DTOR_DTOMUL_4096 (0x5u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 4096 00101 #define HSMCI_DTOR_DTOMUL_65536 (0x6u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 65536 00102 #define HSMCI_DTOR_DTOMUL_1048576 (0x7u << HSMCI_DTOR_DTOMUL_SHIFT) ///< (HSMCI_DTOR) DTOCYC x 1048576 00103 00104 00105 00106 /* HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register */ 00107 #define HSMCI_SDCR_SDCSEL_MASK 0x3 ///< (HSMCI_SDCR) SDCard/SDIO Slot 00108 #define HSMCI_SDCR_SDCSEL_SLOTA 0x0 ///< (HSMCI_SDCR) Slot A is selected. 00109 #define HSMCI_SDCR_SDCSEL_SLOTB 0x1 ///< (HSMCI_SDCR) SDCARD/SDIO Slot B selected 00110 #define HSMCI_SDCR_SDCSEL_SLOTC 0x2 ///< (HSMCI_SDCR) - 00111 #define HSMCI_SDCR_SDCSEL_SLOTD 0x3 ///< (HSMCI_SDCR) - 00112 #define HSMCI_SDCR_SDCBUS_SHIFT 6 00113 #define HSMCI_SDCR_SDCBUS_MASK (0x3u << HSMCI_SDCR_SDCBUS_SHIFT) ///< (HSMCI_SDCR) SDCard/SDIO Bus Width 00114 #define HSMCI_SDCR_SDCBUS_1 (0x0u << HSMCI_SDCR_SDCBUS_SHIFT) ///< (HSMCI_SDCR) 1 bit 00115 #define HSMCI_SDCR_SDCBUS_4 (0x2u << HSMCI_SDCR_SDCBUS_SHIFT) ///< (HSMCI_SDCR) 4 bit 00116 #define HSMCI_SDCR_SDCBUS_8 (0x3u << HSMCI_SDCR_SDCBUS_SHIFT) ///< (HSMCI_SDCR) 8 bit 00117 00118 /* HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register */ 00119 #define HSMCI_CMDR_CMDNB_MASK 0x3f ///< (HSMCI_CMDR) Command Number 00120 #define HSMCI_CMDR_RSPTYP_SHIFT 6 00121 #define HSMCI_CMDR_RSPTYP_MASK (0x3 << HSMCI_CMDR_RSPTYP_SHIFT) ///< (HSMCI_CMDR) Response Type 00122 #define HSMCI_CMDR_RSPTYP_NORESP 0x0 ///< (HSMCI_CMDR) No response. 00123 #define HSMCI_CMDR_RSPTYP_48_BIT (0x1 << HSMCI_CMDR_RSPTYP_SHIFT) ///< (HSMCI_CMDR) 48-bit response. 00124 #define HSMCI_CMDR_RSPTYP_136_BIT (0x2 << HSMCI_CMDR_RSPTYP_SHIFT) ///< (HSMCI_CMDR) 136-bit response. 00125 #define HSMCI_CMDR_RSPTYP_R1B (0x3 << HSMCI_CMDR_RSPTYP_SHIFT) ///< (HSMCI_CMDR) R1b response type 00126 #define HSMCI_CMDR_SPCMD_SHIFT 8 00127 #define HSMCI_CMDR_SPCMD_MASK (0x7 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Special Command 00128 #define HSMCI_CMDR_SPCMD_STD 0 ///< (HSMCI_CMDR) Not a special CMD. 00129 #define HSMCI_CMDR_SPCMD_INIT (0x1 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. 00130 #define HSMCI_CMDR_SPCMD_SYNC (0x2 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 00131 #define HSMCI_CMDR_SPCMD_CE_ATA (0x3 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 00132 #define HSMCI_CMDR_SPCMD_IT_CMD (0x4 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). 00133 #define HSMCI_CMDR_SPCMD_IT_RESP (0x5 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). 00134 #define HSMCI_CMDR_SPCMD_BOR (0x6 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 00135 #define HSMCI_CMDR_SPCMD_EBO (0x7 << HSMCI_CMDR_SPCMD_SHIFT) ///< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. 00136 #define HSMCI_CMDR_OPDCMD 11 ///< (HSMCI_CMDR) Open Drain Command 00137 #define HSMCI_CMDR_MAXLAT 12 ///< (HSMCI_CMDR) Max Latency for Command to Response 00138 #define HSMCI_CMDR_TRCMD_SHIFT 16 00139 #define HSMCI_CMDR_TRCMD_MASK (0x3 << HSMCI_CMDR_TRCMD_SHIFT) ///< (HSMCI_CMDR) Transfer Command 00140 #define HSMCI_CMDR_TRCMD_NO_DATA 0 ///< (HSMCI_CMDR) No data transfer 00141 #define HSMCI_CMDR_TRCMD_START_DATA (0x1 << HSMCI_CMDR_TRCMD_SHIFT) ///< (HSMCI_CMDR) Start data transfer 00142 #define HSMCI_CMDR_TRCMD_STOP_DATA (0x2 << HSMCI_CMDR_TRCMD_SHIFT) ///< (HSMCI_CMDR) Stop data transfer 00143 #define HSMCI_CMDR_TRDIR 18 ///< (HSMCI_CMDR) Transfer Direction 00144 #define HSMCI_CMDR_TRTYP_SHIFT 19 00145 #define HSMCI_CMDR_TRTYP_MASK (0x7 << HSMCI_CMDR_TRTYP_SHIFT) ///< (HSMCI_CMDR) Transfer Type 00146 #define HSMCI_CMDR_TRTYP_SINGLE 0 ///< (HSMCI_CMDR) MMC/SDCard Single Block 00147 #define HSMCI_CMDR_TRTYP_MULTIPLE (0x1 << HSMCI_CMDR_TRTYP_SHIFT) ///< (HSMCI_CMDR) MMC/SDCard Multiple Block 00148 #define HSMCI_CMDR_TRTYP_STREAM (0x2 << HSMCI_CMDR_TRTYP_SHIFT) ///< (HSMCI_CMDR) MMC Stream 00149 #define HSMCI_CMDR_TRTYP_BYTE (0x4 << HSMCI_CMDR_TRTYP_SHIFT) ///< (HSMCI_CMDR) SDIO Byte 00150 #define HSMCI_CMDR_TRTYP_BLOCK (0x5 << HSMCI_CMDR_TRTYP_SHIFT) ///< (HSMCI_CMDR) SDIO Block 00151 #define HSMCI_CMDR_IOSPCMD_SHIFT 24 00152 #define HSMCI_CMDR_IOSPCMD_MASK (0x3 << HSMCI_CMDR_IOSPCMD_SHIFT) ///< (HSMCI_CMDR) SDIO Special Command 00153 #define HSMCI_CMDR_IOSPCMD_STD (0x0 << HSMCI_CMDR_IOSPCMD_SHIFT) ///< (HSMCI_CMDR) Not an SDIO Special Command 00154 #define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1 << HSMCI_CMDR_IOSPCMD_SHIFT) ///< (HSMCI_CMDR) SDIO Suspend Command 00155 #define HSMCI_CMDR_IOSPCMD_RESUME (0x2 << HSMCI_CMDR_IOSPCMD_SHIFT) ///< (HSMCI_CMDR) SDIO Resume Command 00156 #define HSMCI_CMDR_ATACS 26 ///< (HSMCI_CMDR) ATA with Command Completion Signal 00157 #define HSMCI_CMDR_BOOT_ACK 27 ///< (HSMCI_CMDR) Boot Operation Acknowledge. 00158 00159 00160 /* HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register */ 00161 #define HSMCI_BLKR_BCNT_MASK 0xffff ///< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count 00162 #define HSMCI_BLKR_BCNT_MULTIPLE 0x0 ///< (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. 00163 #define HSMCI_BLKR_BCNT_BYTE 0x4 ///< (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. 00164 #define HSMCI_BLKR_BCNT_BLOCK 0x5 ///< (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. 00165 #define HSMCI_BLKR_BLKLEN_MASK 0xffff0000 ///< (HSMCI_BLKR) Data Block Length 00166 #define HSMCI_BLKR_BLKLEN_SHIFT 16 00167 00168 00169 /* HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register */ 00170 #define HSMCI_CSTOR_CSTOCYC_MASK 0xf ///< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number 00171 #define HSMCI_CSTOR_CSTOMUL_SHIFT 4 00172 #define HSMCI_CSTOR_CSTOMUL_MASK (0x7 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) Completion Signal Timeout Multiplier 00173 #define HSMCI_CSTOR_CSTOMUL_1 (0x0 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 1 00174 #define HSMCI_CSTOR_CSTOMUL_16 (0x1 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 16 00175 #define HSMCI_CSTOR_CSTOMUL_128 (0x2 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 128 00176 #define HSMCI_CSTOR_CSTOMUL_256 (0x3 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 256 00177 #define HSMCI_CSTOR_CSTOMUL_1024 (0x4 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 1024 00178 #define HSMCI_CSTOR_CSTOMUL_4096 (0x5 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 4096 00179 #define HSMCI_CSTOR_CSTOMUL_65536 (0x6 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 65536 00180 #define HSMCI_CSTOR_CSTOMUL_1048576 (0x7 << HSMCI_CSTOR_CSTOMUL_SHIFT) ///< (HSMCI_CSTOR) CSTOCYC x 1048576 00181 00182 /* HSMCI_SR : (HSMCI Offset: 0x40) Status Register */ 00183 #define HSMCI_SR_CMDRDY 0 ///< (HSMCI_SR) Command Ready 00184 #define HSMCI_SR_RXRDY 1 ///< (HSMCI_SR) Receiver Ready 00185 #define HSMCI_SR_TXRDY 2 ///< (HSMCI_SR) Transmit Ready 00186 #define HSMCI_SR_BLKE 3 ///< (HSMCI_SR) Data Block Ended 00187 #define HSMCI_SR_DTIP 4 ///< (HSMCI_SR) Data Transfer in Progress 00188 #define HSMCI_SR_NOTBUSY 5 ///< (HSMCI_SR) HSMCI Not Busy 00189 #define HSMCI_SR_SDIOIRQforSlotA 8 ///< (HSMCI_SR) 00190 #define HSMCI_SR_SDIOIRQforSlotB 9 ///< (HSMCI_SR) 00191 #define HSMCI_SR_SDIOWAIT 12 ///< (HSMCI_SR) SDIO Read Wait Operation Status 00192 #define HSMCI_SR_CSRCV 13 ///< (HSMCI_SR) CE-ATA Completion Signal Received 00193 #define HSMCI_SR_RINDE 16 ///< (HSMCI_SR) Response Index Error 00194 #define HSMCI_SR_RDIRE 17 ///< (HSMCI_SR) Response Direction Error 00195 #define HSMCI_SR_RCRCE 18 ///< (HSMCI_SR) Response CRC Error 00196 #define HSMCI_SR_RENDE 19 ///< (HSMCI_SR) Response End Bit Error 00197 #define HSMCI_SR_RTOE 20 ///< (HSMCI_SR) Response Time-out Error 00198 #define HSMCI_SR_DCRCE 21 ///< (HSMCI_SR) Data CRC Error 00199 #define HSMCI_SR_DTOE 22 ///< (HSMCI_SR) Data Time-out Error 00200 #define HSMCI_SR_CSTOE 23 ///< (HSMCI_SR) Completion Signal Time-out Error 00201 #define HSMCI_SR_BLKOVRE 24 ///< (HSMCI_SR) DMA Block Overrun Error 00202 #define HSMCI_SR_DMADONE 25 ///< (HSMCI_SR) DMA Transfer done 00203 #define HSMCI_SR_FIFOEMPTY 26 ///< (HSMCI_SR) FIFO empty flag 00204 #define HSMCI_SR_XFRDONE 27 ///< (HSMCI_SR) Transfer Done flag 00205 #define HSMCI_SR_ACKRCV 28 ///< (HSMCI_SR) Boot Operation Acknowledge Received 00206 #define HSMCI_SR_ACKRCVE 29 ///< (HSMCI_SR) Boot Operation Acknowledge Error 00207 #define HSMCI_SR_OVRE 30 ///< (HSMCI_SR) Overrun 00208 #define HSMCI_SR_UNRE 31 ///< (HSMCI_SR) Underrun 00209 00210 00211 /* HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register */ 00212 #define HSMCI_IER_CMDRDY 0 ///< (HSMCI_IER) Command Ready Interrupt Enable 00213 #define HSMCI_IER_RXRDY 1 ///< (HSMCI_IER) Receiver Ready Interrupt Enable 00214 #define HSMCI_IER_TXRDY 2 ///< (HSMCI_IER) Transmit Ready Interrupt Enable 00215 #define HSMCI_IER_BLKE 3 ///< (HSMCI_IER) Data Block Ended Interrupt Enable 00216 #define HSMCI_IER_DTIP 4 ///< (HSMCI_IER) Data Transfer in Progress Interrupt Enable 00217 #define HSMCI_IER_NOTBUSY 5 ///< (HSMCI_IER) Data Not Busy Interrupt Enable 00218 #define HSMCI_IER_SDIOIRQforSlotA 8 ///< (HSMCI_IER) 00219 #define HSMCI_IER_SDIOIRQforSlotB 9 ///< (HSMCI_IER) 00220 #define HSMCI_IER_SDIOWAIT 12 ///< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable 00221 #define HSMCI_IER_CSRCV 13 ///< (HSMCI_IER) Completion Signal Received Interrupt Enable 00222 #define HSMCI_IER_RINDE 16 ///< (HSMCI_IER) Response Index Error Interrupt Enable 00223 #define HSMCI_IER_RDIRE 17 ///< (HSMCI_IER) Response Direction Error Interrupt Enable 00224 #define HSMCI_IER_RCRCE 18 ///< (HSMCI_IER) Response CRC Error Interrupt Enable 00225 #define HSMCI_IER_RENDE 19 ///< (HSMCI_IER) Response End Bit Error Interrupt Enable 00226 #define HSMCI_IER_RTOE 20 ///< (HSMCI_IER) Response Time-out Error Interrupt Enable 00227 #define HSMCI_IER_DCRCE 21 ///< (HSMCI_IER) Data CRC Error Interrupt Enable 00228 #define HSMCI_IER_DTOE 22 ///< (HSMCI_IER) Data Time-out Error Interrupt Enable 00229 #define HSMCI_IER_CSTOE 23 ///< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable 00230 #define HSMCI_IER_BLKOVRE 24 ///< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable 00231 #define HSMCI_IER_DMADONE 25 ///< (HSMCI_IER) DMA Transfer completed Interrupt Enable 00232 #define HSMCI_IER_FIFOEMPTY 26 ///< (HSMCI_IER) FIFO empty Interrupt enable 00233 #define HSMCI_IER_XFRDONE 27 ///< (HSMCI_IER) Transfer Done Interrupt enable 00234 #define HSMCI_IER_ACKRCV 28 ///< (HSMCI_IER) Boot Acknowledge Interrupt Enable 00235 #define HSMCI_IER_ACKRCVE 29 ///< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable 00236 #define HSMCI_IER_OVRE 30 ///< (HSMCI_IER) Overrun Interrupt Enable 00237 #define HSMCI_IER_UNRE 31 ///< (HSMCI_IER) Underrun Interrupt Enable 00238 00239 00240 /* HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register */ 00241 #define HSMCI_IDR_CMDRDY 0 ///< (HSMCI_IDR) Command Ready Interrupt Disable 00242 #define HSMCI_IDR_RXRDY 1 ///< (HSMCI_IDR) Receiver Ready Interrupt Disable 00243 #define HSMCI_IDR_TXRDY 2 ///< (HSMCI_IDR) Transmit Ready Interrupt Disable 00244 #define HSMCI_IDR_BLKE 3 ///< (HSMCI_IDR) Data Block Ended Interrupt Disable 00245 #define HSMCI_IDR_DTIP 4 ///< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable 00246 #define HSMCI_IDR_NOTBUSY 5 ///< (HSMCI_IDR) Data Not Busy Interrupt Disable 00247 #define HSMCI_IDR_SDIOIRQforSlotA 8 ///< (HSMCI_IDR) 00248 #define HSMCI_IDR_SDIOIRQforSlotB 9 ///< (HSMCI_IDR) 00249 #define HSMCI_IDR_SDIOWAIT 12 ///< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable 00250 #define HSMCI_IDR_CSRCV 13 ///< (HSMCI_IDR) Completion Signal received interrupt Disable 00251 #define HSMCI_IDR_RINDE 16 ///< (HSMCI_IDR) Response Index Error Interrupt Disable 00252 #define HSMCI_IDR_RDIRE 17 ///< (HSMCI_IDR) Response Direction Error Interrupt Disable 00253 #define HSMCI_IDR_RCRCE 18 ///< (HSMCI_IDR) Response CRC Error Interrupt Disable 00254 #define HSMCI_IDR_RENDE 19 ///< (HSMCI_IDR) Response End Bit Error Interrupt Disable 00255 #define HSMCI_IDR_RTOE 20 ///< (HSMCI_IDR) Response Time-out Error Interrupt Disable 00256 #define HSMCI_IDR_DCRCE 21 ///< (HSMCI_IDR) Data CRC Error Interrupt Disable 00257 #define HSMCI_IDR_DTOE 22 ///< (HSMCI_IDR) Data Time-out Error Interrupt Disable 00258 #define HSMCI_IDR_CSTOE 23 ///< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable 00259 #define HSMCI_IDR_BLKOVRE 24 ///< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable 00260 #define HSMCI_IDR_DMADONE 25 ///< (HSMCI_IDR) DMA Transfer completed Interrupt Disable 00261 #define HSMCI_IDR_FIFOEMPTY 26 ///< (HSMCI_IDR) FIFO empty Interrupt Disable 00262 #define HSMCI_IDR_XFRDONE 27 ///< (HSMCI_IDR) Transfer Done Interrupt Disable 00263 #define HSMCI_IDR_ACKRCV 28 ///< (HSMCI_IDR) Boot Acknowledge Interrupt Disable 00264 #define HSMCI_IDR_ACKRCVE 29 ///< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable 00265 #define HSMCI_IDR_OVRE 30 ///< (HSMCI_IDR) Overrun Interrupt Disable 00266 #define HSMCI_IDR_UNRE 31 ///< (HSMCI_IDR) Underrun Interrupt Disable 00267 00268 /* HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register */ 00269 #define HSMCI_IMR_CMDRDY 0 ///< (HSMCI_IMR) Command Ready Interrupt Mask 00270 #define HSMCI_IMR_RXRDY 1 ///< (HSMCI_IMR) Receiver Ready Interrupt Mask 00271 #define HSMCI_IMR_TXRDY 2 ///< (HSMCI_IMR) Transmit Ready Interrupt Mask 00272 #define HSMCI_IMR_BLKE 3 ///< (HSMCI_IMR) Data Block Ended Interrupt Mask 00273 #define HSMCI_IMR_DTIP 4 ///< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask 00274 #define HSMCI_IMR_NOTBUSY 5 ///< (HSMCI_IMR) Data Not Busy Interrupt Mask 00275 #define HSMCI_IMR_SDIOIRQforSlotA 8 ///< (HSMCI_IMR) 00276 #define HSMCI_IMR_SDIOIRQforSlotB 9 ///< (HSMCI_IMR) 00277 #define HSMCI_IMR_SDIOWAIT 12 ///< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask 00278 #define HSMCI_IMR_CSRCV 13 ///< (HSMCI_IMR) Completion Signal Received Interrupt Mask 00279 #define HSMCI_IMR_RINDE 16 ///< (HSMCI_IMR) Response Index Error Interrupt Mask 00280 #define HSMCI_IMR_RDIRE 17 ///< (HSMCI_IMR) Response Direction Error Interrupt Mask 00281 #define HSMCI_IMR_RCRCE 18 ///< (HSMCI_IMR) Response CRC Error Interrupt Mask 00282 #define HSMCI_IMR_RENDE 19 ///< (HSMCI_IMR) Response End Bit Error Interrupt Mask 00283 #define HSMCI_IMR_RTOE 20 ///< (HSMCI_IMR) Response Time-out Error Interrupt Mask 00284 #define HSMCI_IMR_DCRCE 21 ///< (HSMCI_IMR) Data CRC Error Interrupt Mask 00285 #define HSMCI_IMR_DTOE 22 ///< (HSMCI_IMR) Data Time-out Error Interrupt Mask 00286 #define HSMCI_IMR_CSTOE 23 ///< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask 00287 #define HSMCI_IMR_BLKOVRE 24 ///< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask 00288 #define HSMCI_IMR_DMADONE 25 ///< (HSMCI_IMR) DMA Transfer Completed Interrupt Mask 00289 #define HSMCI_IMR_FIFOEMPTY 26 ///< (HSMCI_IMR) FIFO Empty Interrupt Mask 00290 #define HSMCI_IMR_XFRDONE 27 ///< (HSMCI_IMR) Transfer Done Interrupt Mask 00291 #define HSMCI_IMR_ACKRCV 28 ///< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask 00292 #define HSMCI_IMR_ACKRCVE 29 ///< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask 00293 #define HSMCI_IMR_OVRE 30 ///< (HSMCI_IMR) Overrun Interrupt Mask 00294 #define HSMCI_IMR_UNRE 31 ///< (HSMCI_IMR) Underrun Interrupt Mask 00295 00296 00297 /* HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register */ 00298 #define HSMCI_DMA_OFFSET_MASK 0x3 ///< (HSMCI_DMA) DMA Write Buffer Offset 00299 #define HSMCI_DMA_CHKSIZE 4 ///< (HSMCI_DMA) DMA Channel Read and Write Chunk Size 00300 #define HSMCI_DMA_DMAEN 8 ///< (HSMCI_DMA) DMA Hardware Handshaking Enable 00301 #define HSMCI_DMA_ROPT 12 ///< (HSMCI_DMA) Read Optimization with padding 00302 00303 00304 /* HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register */ 00305 #define HSMCI_CFG_FIFOMODE 0 ///< (HSMCI_CFG) HSMCI Internal FIFO control mode 00306 #define HSMCI_CFG_FERRCTRL 4 ///< (HSMCI_CFG) Flow Error flag reset control mode 00307 #define HSMCI_CFG_HSMODE 8 ///< (HSMCI_CFG) High Speed Mode 00308 #define HSMCI_CFG_LSYNC 12 ///< (HSMCI_CFG) Synchronize on the last block 00309 00310 /* HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register */ 00311 #define HSMCI_WPMR_WP_EN 0 ///< (HSMCI_WPMR) Write Protection Enable 00312 #define HSMCI_WPMR_WP_KEY_MASK 0xffffff00 ///< (HSMCI_WPMR) Write Protection Key password 00313 00314 /* HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register */ 00315 #define HSMCI_WPSR_WP_VS_MASK 0xf ///< (HSMCI_WPSR) Write Protection Violation Status 00316 #define HSMCI_WPSR_WP_VS_NONE 0x0 ///< (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) 00317 #define HSMCI_WPSR_WP_VS_WRITE 0x1 ///< (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) 00318 #define HSMCI_WPSR_WP_VS_RESET 0x2 ///< (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). 00319 #define HSMCI_WPSR_WP_VS_BOTH 0x3 ///< (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. 00320 #define HSMCI_WPSR_WP_VSRC_MASK 0xffff00 ///< (HSMCI_WPSR) Write Protection Violation SouRCe 00321 00322 #endif /* SAM3_HSMCI_H */
