00001
00038 #ifndef SAM3_PDC_H
00039 #define SAM3_PDC_H
00040 
00041
00045 #define PERIPH_RPR_OFF                     0x100 ///< Receive Pointer Register.
00046 #define PERIPH_RCR_OFF                     0x104 ///< Receive Counter Register.
00047 #define PERIPH_TPR_OFF                     0x108 ///< Transmit Pointer Register.
00048 #define PERIPH_TCR_OFF                     0x10C ///< Transmit Counter Register.
00049 #define PERIPH_RNPR_OFF                    0x110 ///< Receive Next Pointer Register.
00050 #define PERIPH_RNCR_OFF                    0x114 ///< Receive Next Counter Register.
00051 #define PERIPH_TNPR_OFF                    0x118 ///< Transmit Next Pointer Register.
00052 #define PERIPH_TNCR_OFF                    0x11C ///< Transmit Next Counter Register.
00053 #define PERIPH_PTCR_OFF                    0x120 ///< Transfer Control Register.
00054 #define PERIPH_PTSR_OFF                    0x124 ///< Transfer Status Register.
00055 
00056
00057 #define PDC_PTCR_RXTEN               0  ///< Receiver Transfer Enable.
00058 #define PDC_PTCR_RXTDIS              1  ///< Receiver Transfer Disable.
00059 #define PDC_PTCR_TXTEN               8  ///< Transmitter Transfer Enable.
00060 #define PDC_PTCR_TXTDIS              9  ///< Transmitter Transfer Disable.
00061 #define PDC_PTSR_RXTEN               0  ///< Receiver Transfer Enable.
00062 #define PDC_PTSR_TXTEN               8  ///< Transmitter Transfer Enable.
00063 
00064
00065 #endif /* SAM3_PDC_H */