00001
00036 #ifndef SAM3_PMC_H
00037 #define SAM3_PMC_H
00038 
00039 #include <cfg/macros.h>
00040 #include <cfg/debug.h>
00041
00042
00044 #if CPU_CM3_SAM3X
00045     #define PMC_BASE  0x400E0600
00046 #else
00047     #define PMC_BASE  0x400E0400
00048 #endif
00049 
00053 /*\{*/
00054 #define PMC_SCER_OFF  0x00         ///< System Clock Enable Register
00055 #define PMC_SCDR_OFF  0x04         ///< System Clock Disable Register
00056 #define PMC_SCSR_OFF  0x08         ///< System Clock Status Register
00057 #define PMC_MOR_OFF   0x20         ///< Main Oscillator Register
00058 #define PMC_MCFR_OFF  0x24         ///< Main Clock Frequency Register
00059 #define PMC_MCKR_OFF  0x30         ///< Master Clock Register
00060 #define PMC_IER_OFF   0x60         ///< Interrupt Enable Register
00061 #define PMC_IDR_OFF   0x64         ///< Interrupt Disable Register
00062 #define PMC_SR_OFF    0x68         ///< Status Register
00063 #define PMC_IMR_OFF   0x6C         ///< Interrupt Mask Register
00064 #define PMC_FSMR_OFF  0x70         ///< Fast Startup Mode Register
00065 #define PMC_FSPR_OFF  0x74         ///< Fast Startup Polarity Register
00066 #define PMC_FOCR_OFF  0x78         ///< Fault Output Clear Register
00067 #define PMC_WPMR_OFF  0xE4         ///< Write Protect Mode Register
00068 #define PMC_WPSR_OFF  0xE8         ///< Write Protect Status Register
00069 
00070 #if CPU_CM3_SAM3N
00071     #define PMC_PCER_OFF   0x10    ///< Peripheral Clock Enable Register
00072     #define PMC_PCDR_OFF   0x14    ///< Peripheral Clock Disable Register
00073     #define PMC_PCSR_OFF   0x18    ///< Peripheral Clock Status Register
00074     #define PMC_PLLR_OFF   0x28    ///< PLL Register
00075     #define PMC_PCK_OFF    0x40    ///< Programmable Clock 0 Register
00076     #define PMC_OCR_OFF    0x110   ///< Oscillator Calibration Register
00077 #elif CPU_CM3_SAM3X
00078     #define PMC_PCER0_OFF  0x10    ///< Peripheral Clock Enable Register
00079     #define PMC_PCDR0_OFF  0x14    ///< Peripheral Clock Disable Register
00080     #define PMC_PCSR0_OFF  0x18    ///< Peripheral Clock Status Register
00081     #define PMC_UCKR_OFF   0x1C    ///< UTMI clock register
00082     #define PMC_PLLAR_OFF  0x28    ///< PLL Register
00083     #define PMC_USB_OFF    0x38    ///< USB clock register
00084     #define PMC_PCK0_OFF   0x40    ///< Programmable Clock 0 Register
00085     #define PMC_PCK1_OFF   0x44    ///< Programmable Clock 1 Register
00086     #define PMC_PCK2_OFF   0x48    ///< Programmable Clock 2 Register
00087     #define PMC_PCER1_OFF  0x100   ///< Peripheral Clock Enable Register
00088     #define PMC_PCDR1_OFF  0x104   ///< Peripheral Clock Disable Register
00089     #define PMC_PCSR1_OFF  0x108   ///< Peripheral Clock Status Register
00090     #define PMC_PCR_OFF    0x10C   ///< Oscillator Calibration Register
00091 
00092     #define PMC_PLLROFF    PMC_PLLAR_OFF
00093 #else
00094     #warning Some PMC registers undefined for the selected CPU
00095 #endif
00096 /*\}*/
00097
00098
00103 #define  PMC_PCK0_ID   8
00104 #define  PMC_PCK1_ID   9
00105 #define  PMC_PCK2_ID  10
00106 /*\}*/
00107
00112 #define PMC_PCKRDY0                          8  ///< Programmable clock 0 ready.
00113 #define PMC_PCKRDY1                          9  ///< Programmable clock 1 ready.
00114 #define PMC_PCKRDY2                         10  ///< Programmable clock 2 ready.
00115 /*\}*/
00116
00120 /*\{*/
00121 #define PMC_SCER  (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))   ///< System Clock Enable Register
00122 #define PMC_SCDR  (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF)))   ///< System Clock Disable Register
00123 #define PMC_SCSR  (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF)))   ///< System Clock Status Register
00124 #define CKGR_MOR  (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF )))   ///< Main Oscillator Register
00125 #define CKGR_MCFR (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF)))   ///< Main Clock Frequency Register
00126 #define PMC_MCKR  (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF)))   ///< Master Clock Register
00127 #define PMC_IER   (*((reg32_t *)(PMC_BASE + PMC_IER_OFF )))   ///< Interrupt Enable Register
00128 #define PMC_IDR   (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF )))   ///< Interrupt Disable Register
00129 #define PMC_SR    (*((reg32_t *)(PMC_BASE + PMC_SR_OFF  )))   ///< Status Register
00130 #define PMC_IMR   (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF )))   ///< Interrupt Mask Register
00131 #define PMC_FSMR  (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF)))   ///< Fast Startup Mode Register
00132 #define PMC_FSPR  (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF)))   ///< Fast Startup Polarity Register
00133 #define PMC_FOCR  (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF)))   ///< Fault Output Clear Register
00134 #define PMC_WPMR  (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF)))   ///< Write Protect Mode Register
00135 #define PMC_WPSR  (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF)))   ///< Write Protect Status Register
00136 
00137 #if CPU_CM3_SAM3N
00138     #define PMC_PCER   (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF)))  ///< Peripheral Clock Enable Register
00139     #define PMC_PCDR   (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF)))  ///< Peripheral Clock Disable Register
00140     #define PMC_PCSR   (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF)))  ///< Peripheral Clock Status Register
00141     #define CKGR_PLLR  (*((reg32_t *)(PMC_BASE + PMC_PLLR_OFF)))  ///< PLL Register
00142     #define PMC_PCK    (*((reg32_t *)(PMC_BASE + PMC_PCK_OFF )))  ///< Programmable Clock 0 Register
00143     #define PMC_OCR    (*((reg32_t *)(PMC_BASE + PMC_OCR_OFF )))  ///< Oscillator Calibration Register
00144 #elif CPU_CM3_SAM3X
00145     #define PMC_PCER0  (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF)))     ///< Peripheral Clock Enable Register
00146     #define PMC_PCDR0  (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF)))     ///< Peripheral Clock Disable Register
00147     #define PMC_PCSR0  (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF)))     ///< Peripheral Clock Status Register
00148     #define PMC_UCKR   (*((reg32_t *)(PMC_BASE + PMC_UCKR_OFF)))     ///< UTMI clock register
00149     #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF)))     ///< PLL Register
00150     #define PMC_USB_O  (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF)))     ///< USB clock register
00151     #define PMC_PCK0   (*((reg32_t *)(PMC_BASE + PMC_PCK0_OFF)))     ///< Programmable Clock 0 Register
00152     #define PMC_PCK1   (*((reg32_t *)(PMC_BASE + PMC_PCK1_OFF)))     ///< Programmable Clock 1 Register
00153     #define PMC_PCK2   (*((reg32_t *)(PMC_BASE + PMC_PCK2_OFF)))     ///< Programmable Clock 2 Register
00154     #define PMC_PCER1  (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF)))     ///< Peripheral Clock Enable Register
00155     #define PMC_PCDR1  (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF)))     ///< Peripheral Clock Disable Register
00156     #define PMC_PCSR1  (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF)))     ///< Peripheral Clock Status Register
00157     #define PMC_PCR    (*((reg32_t *)(PMC_BASE + PMC_PCR_OFF)))     ///< Oscillator Calibration Register
00158 
00159     #define CKGR_PLLR  CKGR_PLLAR
00160 #endif
00161 /*\}*/
00162
00168 #ifdef PMC_PCER1
00169 
00170 INLINE void pmc_periphEnable(unsigned id)
00171 {
00172     ASSERT(id < 64);
00173     if (id < 32)
00174         PMC_PCER0 = BV(id);
00175     else
00176         PMC_PCER1 = BV(id - 32);
00177 }
00178
00179 #else
00180 
00181 INLINE void pmc_periphEnable(unsigned id)
00182 {
00183     ASSERT(id < 32);
00184     PMC_PCER = BV(id);
00185 }
00186
00187 #endif
00188 
00194 #ifdef PMC_PCER1
00195 
00196 INLINE void pmc_periphDisable(unsigned id)
00197 {
00198     ASSERT(id < 64);
00199     if (id < 32)
00200         PMC_PCDR0 = BV(id);
00201     else
00202         PMC_PCDR1 = BV(id - 32);
00203 }
00204
00205 #else
00206 
00207 INLINE void pmc_periphDisable(unsigned id)
00208 {
00209     ASSERT(id < 32);
00210     PMC_PCDR = BV(id);
00211 }
00212
00213 #endif
00214 
00218 /*\{*/
00219 #define PMC_SCER_PCK0  8   ///< Programmable Clock 0 Output Enable
00220 #define PMC_SCER_PCK1  9   ///< Programmable Clock 1 Output Enable
00221 #define PMC_SCER_PCK2  10  ///< Programmable Clock 2 Output Enable
00222 /*\}*/
00223
00227 /*\{*/
00228 #define PMC_SCDR_PCK0  8   ///< Programmable Clock 0 Output Disable
00229 #define PMC_SCDR_PCK1  9   ///< Programmable Clock 1 Output Disable
00230 #define PMC_SCDR_PCK2  10  ///< Programmable Clock 2 Output Disable
00231 /*\}*/
00232
00236 /*\{*/
00237 #define PMC_SCSR_PCK0  8   ///< Programmable Clock 0 Output Status
00238 #define PMC_SCSR_PCK1  9   ///< Programmable Clock 1 Output Status
00239 #define PMC_SCSR_PCK2  10  ///< Programmable Clock 2 Output Status
00240 /*\}*/
00241
00245 /*\{*/
00246 #define CKGR_MOR_MOSCXTEN         0   ///< Main Crystal Oscillator Enable
00247 #define CKGR_MOR_MOSCXTBY         1   ///< Main Crystal Oscillator Bypass
00248 #define CKGR_MOR_WAITMODE         2   ///< Wait Mode Command
00249 #define CKGR_MOR_MOSCRCEN         3   ///< Main On-Chip RC Oscillator Enable
00250 #define CKGR_MOR_MOSCRCF_SHIFT    4
00251 #define CKGR_MOR_MOSCRCF_MASK     (0x7 << CKGR_MOR_MOSCRCF_SHIFT)   ///< Main On-Chip RC Oscillator Frequency Selection
00252 #define CKGR_MOR_MOSCRCF(value)   ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
00253 #define CKGR_MOR_MOSCRCF_4MHZ   (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
00254 #define CKGR_MOR_MOSCRCF_8MHZ   (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
00255 #define CKGR_MOR_MOSCRCF_12MHZ  (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
00256 #define CKGR_MOR_MOSCXTST_SHIFT   8
00257 #define CKGR_MOR_MOSCXTST_MASK    (0xff << CKGR_MOR_MOSCXTST_SHIFT)   ///< Main Crystal Oscillator Start-up Time
00258 #define CKGR_MOR_MOSCXTST(value)  ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
00259 #define CKGR_MOR_KEY_SHIFT        16
00260 #define CKGR_MOR_KEY_MASK         (0xffu << CKGR_MOR_KEY_SHIFT)   ///< Password
00261 #define CKGR_MOR_KEY(value)       ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))
00262 #define CKGR_MOR_MOSCSEL          24   ///< Main Oscillator Selection
00263 #define CKGR_MOR_CFDEN            25   ///< Clock Failure Detector Enable
00264 /*\}*/
00265
00269 /*\{*/
00270 #define CKGR_MCFR_MAINF_MASK  0xffff    ///< Main Clock Frequency mask
00271 #define CKGR_MCFR_MAINFRDY    16        ///< Main Clock Ready
00272 /*\}*/
00273
00277 /*\{*/
00278 #define CKGR_PLLR_DIV_MASK        0xff   ///< Divider mask
00279 #define CKGR_PLLR_DIV(value)      (CKGR_PLLR_DIV_MASK & (value))
00280 #define CKGR_PLLR_PLLCOUNT_SHIFT  8
00281 #define CKGR_PLLR_PLLCOUNT_MASK   (0x3f << CKGR_PLLR_PLLCOUNT_SHIFT)   ///< PLL Counter mask
00282 #define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))
00283 #define CKGR_PLLR_MUL_SHIFT       16
00284 #define CKGR_PLLR_MUL_MASK        (0x7ff << CKGR_PLLR_MUL_SHIFT)   ///< PLL Multiplier mask
00285 #define CKGR_PLLR_MUL(value)      (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))
00286 #define CKGR_PLLR_STUCKTO1        29
00287 /*\}*/
00288
00292 /*\{*/
00293 #define   PMC_MCKR_CSS_MASK        0x3   ///< Master Clock Source Selection mask
00294 #define   PMC_MCKR_CSS_SLOW_CLK  0x0   ///< Slow Clock is selected
00295 #define   PMC_MCKR_CSS_MAIN_CLK  0x1   ///< Main Clock is selected
00296 #define   PMC_MCKR_CSS_PLL_CLK   0x2   ///< PLL Clock is selected
00297 #define   PMC_MCKR_PRES_SHIFT      4
00298 #define   PMC_MCKR_PRES_MASK       (0x7 << PMC_MCKR_PRES_SHIFT)    ///< Processor Clock Prescaler mask
00299 #define   PMC_MCKR_PRES_CLK      (0x0 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock
00300 #define   PMC_MCKR_PRES_CLK_2    (0x1 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 2
00301 #define   PMC_MCKR_PRES_CLK_4    (0x2 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 4
00302 #define   PMC_MCKR_PRES_CLK_8    (0x3 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 8
00303 #define   PMC_MCKR_PRES_CLK_16   (0x4 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 16
00304 #define   PMC_MCKR_PRES_CLK_32   (0x5 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 32
00305 #define   PMC_MCKR_PRES_CLK_64   (0x6 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 64
00306 #define   PMC_MCKR_PRES_CLK_3    (0x7 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 3
00307 #define   PMC_MCKR_PLLDIV2         12   ///< PLL Divisor by 2
00308 /*\}*/
00309
00313 /*\{*/
00314 #define   PMC_PCK_CSS_MASK     0x7   ///< Master Clock Source Selection mask
00315 #define   PMC_PCK_CSS_SLOW     0x0   ///< Slow Clock is selected
00316 #define   PMC_PCK_CSS_MAIN     0x1   ///< Main Clock is selected
00317 #define   PMC_PCK_CSS_PLL      0x2   ///< PLL Clock is selected
00318 #define   PMC_PCK_CSS_MCK      0x4   ///< Master Clock is selected
00319 #define   PMC_PCK_PRES_SHIFT     4
00320 #define   PMC_PCK_PRES_MASK    (0x7 << PMC_PCK_PRES_SHIFT)   ///< Programmable Clock Prescaler
00321 #define   PMC_PCK_PRES_CLK     (0x0 << PMC_PCK_PRES_SHIFT)   ///< Selected clock
00322 #define   PMC_PCK_PRES_CLK_2   (0x1 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 2
00323 #define   PMC_PCK_PRES_CLK_4   (0x2 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 4
00324 #define   PMC_PCK_PRES_CLK_8   (0x3 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 8
00325 #define   PMC_PCK_PRES_CLK_16  (0x4 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 16
00326 #define   PMC_PCK_PRES_CLK_32  (0x5 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 32
00327 #define   PMC_PCK_PRES_CLK_64  (0x6 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 64
00328 /*\}*/
00329
00333 /*\{*/
00334 #define PMC_IER_MOSCXTS   0   ///< Main Crystal Oscillator Status Interrupt Enable
00335 #define PMC_IER_LOCK      1   ///< PLL Lock Interrupt Enable
00336 #define PMC_IER_MCKRDY    3   ///< Master Clock Ready Interrupt Enable
00337 #define PMC_IER_PCKRDY0   8   ///< Programmable Clock Ready 0 Interrupt Enable
00338 #define PMC_IER_PCKRDY1   9   ///< Programmable Clock Ready 1 Interrupt Enable
00339 #define PMC_IER_PCKRDY2   10  ///< Programmable Clock Ready 2 Interrupt Enable
00340 #define PMC_IER_MOSCSELS  16  ///< Main Oscillator Selection Status Interrupt Enable
00341 #define PMC_IER_MOSCRCS   17  ///< Main On-Chip RC Status Interrupt Enable
00342 #define PMC_IER_CFDEV     18  ///< Clock Failure Detector Event Interrupt Enable
00343 /*\}*/
00344
00348 /*\{*/
00349 #define PMC_IDR_MOSCXTS   0   ///< Main Crystal Oscillator Status Interrupt Disable
00350 #define PMC_IDR_LOCK      1   ///< PLL Lock Interrupt Disable
00351 #define PMC_IDR_MCKRDY    3   ///< Master Clock Ready Interrupt Disable
00352 #define PMC_IDR_PCKRDY0   8   ///< Programmable Clock Ready 0 Interrupt Disable
00353 #define PMC_IDR_PCKRDY1   9   ///< Programmable Clock Ready 1 Interrupt Disable
00354 #define PMC_IDR_PCKRDY2   10  ///< Programmable Clock Ready 2 Interrupt Disable
00355 #define PMC_IDR_MOSCSELS  16  ///< Main Oscillator Selection Status Interrupt Disable
00356 #define PMC_IDR_MOSCRCS   17  ///< Main On-Chip RC Status Interrupt Disable
00357 #define PMC_IDR_CFDEV     18  ///< Clock Failure Detector Event Interrupt Disable
00358 /*\}*/
00359
00363 /*\{*/
00364 #define PMC_SR_MOSCXTS   0   ///< Main XTAL Oscillator Status
00365 #define PMC_SR_LOCK      1   ///< PLL Lock Status
00366 #define PMC_SR_MCKRDY    3   ///< Master Clock Status
00367 #define PMC_SR_OSCSELS   7   ///< Slow Clock Oscillator Selection
00368 #define PMC_SR_PCKRDY0   8   ///< Programmable Clock Ready Status
00369 #define PMC_SR_PCKRDY1   9   ///< Programmable Clock Ready Status
00370 #define PMC_SR_PCKRDY2   10  ///< Programmable Clock Ready Status
00371 #define PMC_SR_MOSCSELS  16  ///< Main Oscillator Selection Status
00372 #define PMC_SR_MOSCRCS   17  ///< Main On-Chip RC Oscillator Status
00373 #define PMC_SR_CFDEV     18  ///< Clock Failure Detector Event
00374 #define PMC_SR_CFDS      19  ///< Clock Failure Detector Status
00375 #define PMC_SR_FOS       20  ///< Clock Failure Detector Fault Output Status
00376 /*\}*/
00377
00381 /*\{*/
00382 #define PMC_IMR_MOSCXTS   0   ///< Main Crystal Oscillator Status Interrupt Mask
00383 #define PMC_IMR_LOCK      1   ///< PLL Lock Interrupt Mask
00384 #define PMC_IMR_MCKRDY    3   ///< Master Clock Ready Interrupt Mask
00385 #define PMC_IMR_PCKRDY0   8   ///< Programmable Clock Ready 0 Interrupt Mask
00386 #define PMC_IMR_PCKRDY1   9   ///< Programmable Clock Ready 1 Interrupt Mask
00387 #define PMC_IMR_PCKRDY2   10  ///< Programmable Clock Ready 2 Interrupt Mask
00388 #define PMC_IMR_MOSCSELS  16  ///< Main Oscillator Selection Status Interrupt Mask
00389 #define PMC_IMR_MOSCRCS   17  ///< Main On-Chip RC Status Interrupt Mask
00390 #define PMC_IMR_CFDEV     18  ///< Clock Failure Detector Event Interrupt Mask
00391 /*\}*/
00392
00396 /*\{*/
00397 #define PMC_FSMR_FSTT0   0   ///< Fast Startup Input Enable 0
00398 #define PMC_FSMR_FSTT1   1   ///< Fast Startup Input Enable 1
00399 #define PMC_FSMR_FSTT2   2   ///< Fast Startup Input Enable 2
00400 #define PMC_FSMR_FSTT3   3   ///< Fast Startup Input Enable 3
00401 #define PMC_FSMR_FSTT4   4   ///< Fast Startup Input Enable 4
00402 #define PMC_FSMR_FSTT5   5   ///< Fast Startup Input Enable 5
00403 #define PMC_FSMR_FSTT6   6   ///< Fast Startup Input Enable 6
00404 #define PMC_FSMR_FSTT7   7   ///< Fast Startup Input Enable 7
00405 #define PMC_FSMR_FSTT8   8   ///< Fast Startup Input Enable 8
00406 #define PMC_FSMR_FSTT9   9   ///< Fast Startup Input Enable 9
00407 #define PMC_FSMR_FSTT10  10  ///< Fast Startup Input Enable 10
00408 #define PMC_FSMR_FSTT11  11  ///< Fast Startup Input Enable 11
00409 #define PMC_FSMR_FSTT12  12  ///< Fast Startup Input Enable 12
00410 #define PMC_FSMR_FSTT13  13  ///< Fast Startup Input Enable 13
00411 #define PMC_FSMR_FSTT14  14  ///< Fast Startup Input Enable 14
00412 #define PMC_FSMR_FSTT15  15  ///< Fast Startup Input Enable 15
00413 #define PMC_FSMR_RTTAL   16  ///< RTT Alarm Enable
00414 #define PMC_FSMR_RTCAL   17  ///< RTC Alarm Enable
00415 #define PMC_FSMR_LPM     20  ///< Low Power Mode
00416 /*\}*/
00417
00421 /*\{*/
00422 #define PMC_FSPR_FSTP0   0   ///< Fast Startup Input Polarityx
00423 #define PMC_FSPR_FSTP1   1   ///< Fast Startup Input Polarityx
00424 #define PMC_FSPR_FSTP2   2   ///< Fast Startup Input Polarityx
00425 #define PMC_FSPR_FSTP3   3   ///< Fast Startup Input Polarityx
00426 #define PMC_FSPR_FSTP4   4   ///< Fast Startup Input Polarityx
00427 #define PMC_FSPR_FSTP5   5   ///< Fast Startup Input Polarityx
00428 #define PMC_FSPR_FSTP6   6   ///< Fast Startup Input Polarityx
00429 #define PMC_FSPR_FSTP7   7   ///< Fast Startup Input Polarityx
00430 #define PMC_FSPR_FSTP8   8   ///< Fast Startup Input Polarityx
00431 #define PMC_FSPR_FSTP9   9   ///< Fast Startup Input Polarityx
00432 #define PMC_FSPR_FSTP10  10  ///< Fast Startup Input Polarityx
00433 #define PMC_FSPR_FSTP11  11  ///< Fast Startup Input Polarityx
00434 #define PMC_FSPR_FSTP12  12  ///< Fast Startup Input Polarityx
00435 #define PMC_FSPR_FSTP13  13  ///< Fast Startup Input Polarityx
00436 #define PMC_FSPR_FSTP14  14  ///< Fast Startup Input Polarityx
00437 #define PMC_FSPR_FSTP15  15  ///< Fast Startup Input Polarityx
00438 /*\}*/
00439
00443 /*\{*/
00444 #define PMC_FOCR_FOCLR  0   ///< Fault Output Clear
00445 /*\}*/
00446
00450 /*\{*/
00451 #define PMC_WPMR_WPEN          0   ///< Write Protect Enable
00452 #define PMC_WPMR_WPKEY_SHIFT   8
00453 #define PMC_WPMR_WPKEY_MASK    (0xffffff << PMC_WPMR_WPKEY_SHIFT)   ///< Write Protect key mask
00454 #define PMC_WPMR_WPKEY(value)  ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))
00455 /*\}*/
00456
00460 /*\{*/
00461 #define PMC_WPSR_WPVS          0   ///< Write Protect Violation Status
00462 #define PMC_WPSR_WPVSRC_SHIFT  8
00463 #define PMC_WPSR_WPVSRC_MASK   (0xffff << PMC_WPSR_WPVSRC_SHIFT)   ///< Write Protect Violation Source mask
00464 /*\}*/
00465
00469 /*\{*/
00470 #define PMC_OCR_CAL4_MASK     0x7f  ///< RC Oscillator Calibration bits for 4 MHz mask
00471 #define PMC_OCR_CAL4(value)   (PMC_OCR_CAL4_MASK & (value))
00472 #define PMC_OCR_SEL4          7   ///< Selection of RC Oscillator Calibration bits for 4 MHz
00473 #define PMC_OCR_CAL8_SHIFT    8
00474 #define PMC_OCR_CAL8_MASK     (0x7f << PMC_OCR_CAL8_SHIFT)   ///< RC Oscillator Calibration bits for 8 MHz mask
00475 #define PMC_OCR_CAL8(value)   ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))
00476 #define PMC_OCR_SEL8          15  ///< Selection of RC Oscillator Calibration bits for 8 MHz
00477 #define PMC_OCR_CAL12_SHIFT   16
00478 #define PMC_OCR_CAL12_MASK    (0x7f << PMC_OCR_CAL12_SHIFT)   ///< RC Oscillator Calibration bits for 12 MHz mask
00479 #define PMC_OCR_CAL12(value)  ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))
00480 #define PMC_OCR_SEL12         23   ///< Selection of RC Oscillator Calibration bits for 12 MHz
00481 /*\}*/
00482
00483
00484 #endif /* SAM3_PMC_H */