![(please configure the [header_logo] section in trac.ini)](/chrome/site/bertos_logo.png){kind=logo}
sam3_ssc.h
Go to the documentation of this file.
00001 00038 #ifndef SAM3_SSC_H 00039 #define SAM3_SSC_H 00040 00041 #include <io/cm3.h> 00042 00044 #define SSC_BASE 0x40004000U 00045 00046 00050 /*\{*/ 00051 #define SSC_CR_OFF 0x00000000 ///< Control register offset. 00052 00053 #define SSC_RXEN 0 ///< Receive enable. 00054 #define SSC_RXDIS 1 ///< Receive disable. 00055 #define SSC_TXEN 8 ///< Transmit enable. 00056 #define SSC_TXDIS 9 ///< Transmit disable. 00057 #define SSC_SWRST 15 ///< Software reset. 00058 /*\}*/ 00059 00063 /*\{*/ 00064 #define SSC_CMR_OFF 0x00000004 ///< Clock mode register offset. 00065 00066 #define SSC_DIV_MASK 0x00000FFF ///< Clock divider. 00067 /*\}*/ 00068 00072 /*\{*/ 00073 #define SSC_RCMR_OFF 0x00000010 ///< Receive clock mode register offset. 00074 #define SSC_TCMR_OFF 0x00000018 ///< Transmit clock mode register offset. 00075 00076 #define SSC_CKS_MASK 0x00000003 ///< Receive clock selection. 00077 #define SSC_CKS_DIV 0x00000000 ///< Divided clock. 00078 #define SSC_CKS_CLK 0x00000001 ///< RK/TK clock signal. 00079 #define SSC_CKS_PIN 0x00000002 ///< TK/RK pin. 00080 #define SSC_CKO_MASK 0x0000001C ///< Receive clock output mode selection. 00081 #define SSC_CKO_NONE 0x00000000 ///< None. 00082 #define SSC_CKO_CONT 0x00000004 ///< Continous receive clock. 00083 #define SSC_CKO_TRAN 0x00000008 ///< Receive clock only during data transfers. 00084 #define SSC_CKI 5 ///< Receive clock inversion. 00085 #define SSC_CKG_MASK 0x000000C0 ///< Receive clock gating selection. 00086 #define SSC_CKG_NONE 0x00000000 ///< None, continous clock. 00087 #define SSC_CKG_FL 0x00000040 ///< Continous receive clock. 00088 #define SSC_CKG_FH 0x00000080 ///< Receive clock only during data transfers. 00089 #define SSC_START_MASK 0x00000F00 ///< Receive start selection. 00090 #define SSC_START_CONT 0x00000000 ///< Receive start as soon as enabled. 00091 #define SSC_START_TX 0x00000100 ///< Receive start on transmit start. 00092 #define SSC_START_RX 0x00000100 ///< Receive start on receive start. 00093 #define SSC_START_LOW_F 0x00000200 ///< Receive start on low level RF. 00094 #define SSC_START_HIGH_F 0x00000300 ///< Receive start on high level RF. 00095 #define SSC_START_FALL_F 0x00000400 ///< Receive start on falling edge RF. 00096 #define SSC_START_RISE_F 0x00000500 ///< Receive start on rising edge RF. 00097 #define SSC_START_LEVEL_F 0x00000600 ///< Receive start on any RF level change. 00098 #define SSC_START_EDGE_F 0x00000700 ///< Receive start on any RF edge. 00099 #define SSC_START_COMP0 0x00000800 ///< Receive on compare 0. 00100 #define SSC_STOP 12 ///< Receive stop selection. 00101 #define SSC_STTDLY_MASK 0x00FF0000 ///< Receive start delay. 00102 #define SSC_STTDLY_SHIFT 16 ///< Least significant bit of receive start delay. 00103 #define SSC_PERIOD_MASK 0xFF000000 ///< Receive period divider selection. 00104 #define SSC_PERIOD_SHIFT 24 ///< Least significant bit of receive period divider selection. 00105 /*\}*/ 00106 00110 /*\{*/ 00111 #define SSC_RFMR_OFF 0x00000014 ///< Receive frame mode register offset. 00112 #define SSC_TFMR_OFF 0x0000001C ///< Transmit frame mode register offset. 00113 00114 #define SSC_DATLEN_MASK 0x0000001F ///< Data length. 00115 #define SSC_LOOP 5 ///< Receiver loop mode. 00116 #define SSC_DATDEF 5 ///< Transmit default value. 00117 00118 #define SSC_MSBF 7 ///< Most significant bit first. 00119 #define SSC_DATNB_MASK 0x00000F00 ///< Data number per frame. 00120 #define SSC_DATNB_SHIFT 8 ///< Least significant bit of data number per frame. 00121 #define SSC_FSLEN_MASK 0x000F0000 ///< Receive frame sync. length. 00122 #define SSC_FSLEN_SHIFT 16 ///< Least significant bit of receive frame sync. length. 00123 #define SSC_FSOS 0x00700000 ///< Receive frame sync. output selection. 00124 #define SSC_FSOS_NONE 0x00000000 ///< No frame sync. Line set to input. 00125 #define SSC_FSOS_NEGATIVE 0x00100000 ///< Negative pulse. 00126 #define SSC_FSOS_POSITIVE 0x00200000 ///< Positive pulse. 00127 #define SSC_FSOS_LOW 0x00300000 ///< Low during transfer. 00128 #define SSC_FSOS_HIGH 0x00400000 ///< High during transfer. 00129 #define SSC_FSOS_TOGGLE 0x00500000 ///< Toggling at each start. 00130 #define SSC_FSDEN 23 ///< Frame sync. data enable. 00131 #define SSC_FSEDGE 24 ///< Frame sync. edge detection. 00132 #define SSC_FSLEN_EXT 26 ///< 00133 /*\}*/ 00134 00138 /*\{*/ 00139 #define SSC_RHR_OFF 0x00000020 ///< Receive holding register offset. 00140 /*\}*/ 00141 00145 /*\{*/ 00146 #define SSC_THR_OFF 0x00000024 ///< Transmit holding register offset. 00147 /*\}*/ 00148 00152 /*\{*/ 00153 #define SSC_RSHR_OFF 0x00000030 ///< Receive sync. holding register offset. 00154 /*\}*/ 00155 00159 /*\{*/ 00160 #define SSC_TSHR_OFF 0x00000034 ///< Transmit sync. holding register offset. 00161 /*\}*/ 00162 00166 /*\{*/ 00167 #define SSC_RC0R_OFF 0x00000038 ///< Receive compare 0 register offset. 00168 /*\}*/ 00169 00173 /*\{*/ 00174 #define SSC_RC1R_OFF 0x0000003C ///< Receive compare 1 register offset. 00175 /*\}*/ 00176 00180 /*\{*/ 00181 #define SSC_SR_OFF 0x00000040 ///< Status register offset. 00182 #define SSC_IER_OFF 0x00000044 ///< Interrupt enable register offset. 00183 #define SSC_IDR_OFF 0x00000048 ///< Interrupt disable register offset. 00184 #define SSC_IMR_OFF 0x0000004C ///< Interrupt mask register offset. 00185 00186 #define SSC_TXRDY 0 ///< Transmit ready. 00187 #define SSC_TXEMPTY 1 ///< Transmit empty. 00188 #define SSC_ENDTX 2 ///< End of transmission. 00189 #define SSC_TXBUFE 3 ///< Transmit buffer empty. 00190 #define SSC_RXRDY 4 ///< Receive ready. 00191 #define SSC_OVRUN 5 ///< Receive overrun. 00192 #define SSC_ENDRX 6 ///< End of receiption. 00193 #define SSC_RXBUFF 7 ///< Receive buffer full. 00194 #define SSC_CP0 8 ///< Compare 0. 00195 #define SSC_CP1 9 ///< Compare 1. 00196 #define SSC_TXSYN 10 ///< Transmit sync. 00197 #define SSC_RXSYN 11 ///< Receive sync. 00198 #define SSC_TXENA 16 ///< Transmit enable. 00199 #define SSC_RXENA 17 ///< Receive enable. 00200 00201 00202 #define SSC_CR (*((reg32_t *)(SSC_BASE + SSC_CR_OFF))) ///< Control register address. 00203 #define SSC_CMR (*((reg32_t *)(SSC_BASE + SSC_CMR_OFF))) ///< Clock mode register address. 00204 #define SSC_RCMR (*((reg32_t *)(SSC_BASE + SSC_RCMR_OFF))) ///< Receive clock mode register address. 00205 #define SSC_TCMR (*((reg32_t *)(SSC_BASE + SSC_TCMR_OFF))) ///< Transmit clock mode register address. 00206 #define SSC_RFMR (*((reg32_t *)(SSC_BASE + SSC_RFMR_OFF))) ///< Receive frame mode register address. 00207 #define SSC_TFMR (*((reg32_t *)(SSC_BASE + SSC_TFMR_OFF))) ///< Transmit frame mode register address. 00208 #define SSC_RHR (*((reg32_t *)(SSC_BASE + SSC_RHR_OFF))) ///< Receive holding register address. 00209 #define SSC_THR (*((reg32_t *)(SSC_BASE + SSC_THR_OFF))) ///< Transmit holding register address. 00210 #define SSC_RSHR (*((reg32_t *)(SSC_BASE + SSC_RSHR_OFF))) ///< Receive sync. holding register address. 00211 #define SSC_TSHR (*((reg32_t *)(SSC_BASE + SSC_TSHR_OFF))) ///< Transmit sync. holding register address. 00212 #define SSC_RC0R (*((reg32_t *)(SSC_BASE + SSC_RC0R_OFF))) ///< Receive compare 0 register address. 00213 #define SSC_RC1R (*((reg32_t *)(SSC_BASE + SSC_RC1R_OFF))) ///< Receive compare 1 register address. 00214 #define SSC_SR (*((reg32_t *)(SSC_BASE + SSC_SR_OFF))) ///< Status register address. 00215 #define SSC_IER (*((reg32_t *)(SSC_BASE + SSC_IER_OFF))) ///< Interrupt enable register address. 00216 #define SSC_IDR (*((reg32_t *)(SSC_BASE + SSC_IDR_OFF))) ///< Interrupt disable register address. 00217 #define SSC_IMR (*((reg32_t *)(SSC_BASE + SSC_IMR_OFF))) ///< Interrupt mask register address. 00218 00219 #define SSC_RPR (*((reg32_t *)(SSC_BASE + PERIPH_RPR_OFF))) ///< Receive pointer register address. 00220 #define SSC_RCR (*((reg32_t *)(SSC_BASE + PERIPH_RCR_OFF))) ///< Receive counter register address. 00221 #define SSC_TPR (*((reg32_t *)(SSC_BASE + PERIPH_TPR_OFF))) ///< Transmit pointer register address. 00222 #define SSC_TCR (*((reg32_t *)(SSC_BASE + PERIPH_TCR_OFF))) ///< Transmit counter register address. 00223 #define SSC_RNPR (*((reg32_t *)(SSC_BASE + PERIPH_RNPR_OFF))) ///< Receive next pointer register address. 00224 #define SSC_RNCR (*((reg32_t *)(SSC_BASE + PERIPH_RNCR_OFF))) ///< Receive next counter register address. 00225 #define SSC_TNPR (*((reg32_t *)(SSC_BASE + PERIPH_TNPR_OFF))) ///< Transmit next pointer register address. 00226 #define SSC_TNCR (*((reg32_t *)(SSC_BASE + PERIPH_TNCR_OFF))) ///< Transmit next counter register address. 00227 #define SSC_PTCR (*((reg32_t *)(SSC_BASE + PERIPH_PTCR_OFF))) ///< Transfer control register address. 00228 #define SSC_PTSR (*((reg32_t *)(SSC_BASE + PERIPH_PTSR_OFF))) ///< Transfer status register address. 00229 00230 #endif /* SAM3_SSC_H */
