SAM3 TWI definitions. More...

Defines

#define	TWI_CR_OFF 0x000
	I2C registers base.
#define	TWI_MMR_OFF 0x004
	I2C registers base.
#define	TWI_SMR_OFF 0x008
	I2C registers base.
#define	TWI_IADR_OFF 0x00C
	I2C registers base.
#define	TWI_CWGR_OFF 0x010
	I2C registers base.
#define	TWI_SR_OFF 0x020
	I2C registers base.
#define	TWI_IER_OFF 0x024
	I2C registers base.
#define	TWI_IDR_OFF 0x028
	I2C registers base.
#define	TWI_IMR_OFF 0x02C
	I2C registers base.
#define	TWI_RHR_OFF 0x030
	I2C registers base.
#define	TWI_THR_OFF 0x034
	I2C registers base.
#define	TWI_RPR_OFF 0x100
	I2C registers base.
#define	TWI_RCR_OFF 0x104
	I2C registers base.
#define	TWI_TPR_OFF 0x108
	I2C registers base.
#define	TWI_TCR_OFF 0x10C
	I2C registers base.
#define	TWI_RNPR_OFF 0x110
	I2C registers base.
#define	TWI_RNCR_OFF 0x114
	I2C registers base.
#define	TWI_TNPR_OFF 0x118
	I2C registers base.
#define	TWI_TNCR_OFF 0x11C
	I2C registers base.
#define	TWI_PTCR_OFF 0x120
	I2C registers base.
#define	TWI_PTSR_OFF 0x124
	I2C registers base.

#define	TWI_CR_START BV(0)
	TWI registers.
#define	TWI_CR_STOP BV(1)
	TWI registers.
#define	TWI_CR_MSEN BV(2)
	TWI registers.
#define	TWI_CR_MSDIS BV(3)
	TWI registers.
#define	TWI_CR_SVEN BV(4)
	TWI registers.
#define	TWI_CR_SVDIS BV(5)
	TWI registers.
#define	TWI_CR_QUICK BV(6)
	TWI registers.
#define	TWI_CR_SWRST BV(7)
	TWI registers.

#define	TWI_MMR_IADRSZ_SHIFT 8
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_IADRSZ_MASK (0x3 << TWI_MMR_IADRSZ_SHIFT)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_IADRSZ_NONE (0x0 << 8)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_IADRSZ_1_BYTE BV(8)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_IADRSZ_2_BYTE (0x2 << 8)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_IADRSZ_3_BYTE (0x3 << 8)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_MREAD BV(12)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_DADR_SHIFT 16
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.
#define	TWI_MMR_DADR(value) ((TWI_MMR_DADR_MASK & ((value) << TWI_MMR_DADR_SHIFT)))
	TWI_MMR: (TWI Offset: 0x04) Master Mode Register.

#define	TWI_SMR_SADR_SHIFT 16
	TWI_SMR: (TWI Offset: 0x08) Slave Mode Register.
#define	TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT)
	TWI_SMR: (TWI Offset: 0x08) Slave Mode Register.
#define	TWI_SMR_SADR(value) ((TWI_SMR_SADR_MASK & ((value) << TWI_SMR_SADR_SHIFT)))
	TWI_SMR: (TWI Offset: 0x08) Slave Mode Register.

#define	TWI_IADR_IADR_SHIFT 0
	TWI_IADR: (TWI Offset: 0x0C) Internal Address Register.
#define	TWI_IADR_IADR_MASK (0xffffff << TWI_IADR_IADR_SHIFT)
	TWI_IADR: (TWI Offset: 0x0C) Internal Address Register.
#define	TWI_IADR_IADR(value) ((TWI_IADR_IADR_MASK & ((value) << TWI_IADR_IADR_SHIFT)))
	TWI_IADR: (TWI Offset: 0x0C) Internal Address Register.

#define	TWI_CWGR_CLDIV_SHIFT 0
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_MASK & ((value) << TWI_CWGR_CLDIV_SHIFT)))
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CHDIV_SHIFT 8
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CHDIV_SHIFT)
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_MASK & ((value) << TWI_CWGR_CHDIV_SHIFT)))
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CKDIV_SHIFT 16
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CKDIV_MASK (0x7 << TWI_CWGR_CKDIV_SHIFT)
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.
#define	TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_MASK & ((value) << TWI_CWGR_CKDIV_SHIFT)))
	TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register.

#define	TWI_SR_TXCOMP BV(0)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_RXRDY BV(1)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_TXRDY BV(2)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_SVREAD BV(3)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_SVACC BV(4)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_GACC BV(5)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_OVRE BV(6)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_NACK BV(8)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_ARBLST BV(9)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_SCLWS BV(10)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_EOSACC BV(11)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_ENDRX BV(12)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_ENDTX BV(13)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_RXBUFF BV(14)
	TWI_SR: (TWI Offset: 0x20) Status Register.
#define	TWI_SR_TXBUFE BV(15)
	TWI_SR: (TWI Offset: 0x20) Status Register.

#define	TWI_IER_TXCOMP BV(0)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_RXRDY BV(1)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_TXRDY BV(2)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_SVACC BV(4)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_GACC BV(5)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_OVRE BV(6)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_NACK BV(8)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_ARBLST BV(9)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_SCL_WS BV(10)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_EOSACC BV(11)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_ENDRX BV(12)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_ENDTX BV(13)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_RXBUFF BV(14)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.
#define	TWI_IER_TXBUFE BV(15)
	TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register.

#define	TWI_IDR_TXCOMP BV(0)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_RXRDY BV(1)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_TXRDY BV(2)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_SVACC BV(4)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_GACC BV(5)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_OVRE BV(6)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_NACK BV(8)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_ARBLST BV(9)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_SCL_WS BV(10)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_EOSACC BV(11)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_ENDRX BV(12)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_ENDTX BV(13)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_RXBUFF BV(14)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.
#define	TWI_IDR_TXBUFE BV(15)
	TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register.

#define	TWI_IMR_TXCOMP BV(0)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_RXRDY BV(1)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_TXRDY BV(2)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_SVACC BV(4)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_GACC BV(5)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_OVRE BV(6)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_NACK BV(8)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_ARBLST BV(9)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_SCL_WS BV(10)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_EOSACC BV(11)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_ENDRX BV(12)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_ENDTX BV(13)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_RXBUFF BV(14)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.
#define	TWI_IMR_TXBUFE BV(15)
	TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register.

#define	TWI_RHR_RXDATA_SHIFT 0
	TWI_RHR: (TWI Offset: 0x30) Receive Holding Register.
#define	TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
	TWI_RHR: (TWI Offset: 0x30) Receive Holding Register.

#define	TWI_THR_TXDATA_SHIFT 0
	TWI_THR: (TWI Offset: 0x34) Transmit Holding Register.
#define	TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
	TWI_THR: (TWI Offset: 0x34) Transmit Holding Register.
#define	TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_MASK & ((value) << TWI_THR_TXDATA_SHIFT)))
	TWI_THR: (TWI Offset: 0x34) Transmit Holding Register.

#define	TWI_RPR_RXPTR_SHIFT 0
	TWI_RPR: (TWI Offset: 0x100) Receive Pointer Register.
#define	TWI_RPR_RXPTR_MASK (0xffffffff << TWI_RPR_RXPTR_SHIFT)
	TWI_RPR: (TWI Offset: 0x100) Receive Pointer Register.
#define	TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_MASK & ((value) << TWI_RPR_RXPTR_SHIFT)))
	TWI_RPR: (TWI Offset: 0x100) Receive Pointer Register.

#define	TWI_RCR_RXCTR_SHIFT 0
	TWI_RCR: (TWI Offset: 0x104) Receive Counter Register.
#define	TWI_RCR_RXCTR_MASK (0xffff << TWI_RCR_RXCTR_SHIFT)
	TWI_RCR: (TWI Offset: 0x104) Receive Counter Register.
#define	TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_MASK & ((value) << TWI_RCR_RXCTR_SHIFT)))
	TWI_RCR: (TWI Offset: 0x104) Receive Counter Register.

#define	TWI_TPR_TXPTR_SHIFT 0
	TWI_TPR: (TWI Offset: 0x108) Transmit Pointer Register.
#define	TWI_TPR_TXPTR_MASK (0xffffffff << TWI_TPR_TXPTR_SHIFT)
	TWI_TPR: (TWI Offset: 0x108) Transmit Pointer Register.
#define	TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_MASK & ((value) << TWI_TPR_TXPTR_SHIFT)))
	TWI_TPR: (TWI Offset: 0x108) Transmit Pointer Register.

#define	TWI_TCR_TXCTR_SHIFT 0
	TWI_TCR: (TWI Offset: 0x10C) Transmit Counter Register.
#define	TWI_TCR_TXCTR_MASK (0xffff << TWI_TCR_TXCTR_SHIFT)
	TWI_TCR: (TWI Offset: 0x10C) Transmit Counter Register.
#define	TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_MASK & ((value) << TWI_TCR_TXCTR_SHIFT)))
	TWI_TCR: (TWI Offset: 0x10C) Transmit Counter Register.

#define	TWI_RNPR_RXNPTR_SHIFT 0
	TWI_RNPR: (TWI Offset: 0x110) Receive Next Pointer Register.
#define	TWI_RNPR_RXNPTR_MASK (0xffffffff << TWI_RNPR_RXNPTR_SHIFT)
	TWI_RNPR: (TWI Offset: 0x110) Receive Next Pointer Register.
#define	TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_MASK & ((value) << TWI_RNPR_RXNPTR_SHIFT)))
	TWI_RNPR: (TWI Offset: 0x110) Receive Next Pointer Register.

#define	TWI_RNCR_RXNCTR_SHIFT 0
	TWI_RNCR: (TWI Offset: 0x114) Receive Next Counter Register.
#define	TWI_RNCR_RXNCTR_MASK (0xffff << TWI_RNCR_RXNCTR_SHIFT)
	TWI_RNCR: (TWI Offset: 0x114) Receive Next Counter Register.
#define	TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_MASK & ((value) << TWI_RNCR_RXNCTR_SHIFT)))
	TWI_RNCR: (TWI Offset: 0x114) Receive Next Counter Register.

#define	TWI_TNPR_TXNPTR_SHIFT 0
	TWI_TNPR: (TWI Offset: 0x118) Transmit Next Pointer Register.
#define	TWI_TNPR_TXNPTR_MASK (0xffffffff << TWI_TNPR_TXNPTR_SHIFT)
	TWI_TNPR: (TWI Offset: 0x118) Transmit Next Pointer Register.
#define	TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_MASK & ((value) << TWI_TNPR_TXNPTR_SHIFT)))
	TWI_TNPR: (TWI Offset: 0x118) Transmit Next Pointer Register.

#define	TWI_TNCR_TXNCTR_SHIFT 0
	TWI_TNCR: (TWI Offset: 0x11C) Transmit Next Counter Register.
#define	TWI_TNCR_TXNCTR_MASK (0xffff << TWI_TNCR_TXNCTR_SHIFT)
	TWI_TNCR: (TWI Offset: 0x11C) Transmit Next Counter Register.
#define	TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_MASK & ((value) << TWI_TNCR_TXNCTR_SHIFT)))
	TWI_TNCR: (TWI Offset: 0x11C) Transmit Next Counter Register.

#define	TWI_PTCR_RXTEN BV(0)
	TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register.
#define	TWI_PTCR_RXTDIS BV(1)
	TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register.
#define	TWI_PTCR_TXTEN BV(8)
	TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register.
#define	TWI_PTCR_TXTDIS BV(9)
	TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register.

#define	TWI_PTSR_RXTEN BV(0)
	TWI_PTSR: (TWI Offset: 0x124) Transfer Status Register.
#define	TWI_PTSR_TXTEN BV(8)
	TWI_PTSR: (TWI Offset: 0x124) Transfer Status Register.

Detailed Description

SAM3 TWI definitions.

Definition in file sam3_twi.h.

Define Documentation

#define TWI_CR_MSDIS BV(3)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 166 of file sam3_twi.h.

#define TWI_CR_MSEN BV(2)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 165 of file sam3_twi.h.

#define TWI_CR_OFF 0x000

I2C registers base.

TWI register offsets.

Definition at line 58 of file sam3_twi.h.

#define TWI_CR_QUICK BV(6)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 169 of file sam3_twi.h.

#define TWI_CR_START BV(0)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 163 of file sam3_twi.h.

#define TWI_CR_STOP BV(1)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 164 of file sam3_twi.h.

#define TWI_CR_SVDIS BV(5)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 168 of file sam3_twi.h.

#define TWI_CR_SVEN BV(4)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 167 of file sam3_twi.h.

#define TWI_CR_SWRST BV(7)

TWI registers.

TWI_CR: (TWI Offset: 0x00) Control Register

Definition at line 170 of file sam3_twi.h.

#define TWI_CWGR_OFF 0x010

I2C registers base.

TWI register offsets.

Definition at line 62 of file sam3_twi.h.

#define TWI_IADR_OFF 0x00C

I2C registers base.

TWI register offsets.

Definition at line 61 of file sam3_twi.h.

#define TWI_IDR_OFF 0x028

I2C registers base.

TWI register offsets.

Definition at line 65 of file sam3_twi.h.

#define TWI_IER_OFF 0x024

I2C registers base.

TWI register offsets.

Definition at line 64 of file sam3_twi.h.

#define TWI_IMR_OFF 0x02C

I2C registers base.

TWI register offsets.

Definition at line 66 of file sam3_twi.h.

#define TWI_MMR_OFF 0x004

I2C registers base.

TWI register offsets.

Definition at line 59 of file sam3_twi.h.

#define TWI_PTCR_OFF 0x120

I2C registers base.

TWI register offsets.

Definition at line 77 of file sam3_twi.h.

#define TWI_PTSR_OFF 0x124

I2C registers base.

TWI register offsets.

Definition at line 78 of file sam3_twi.h.

#define TWI_RCR_OFF 0x104

I2C registers base.

TWI register offsets.

Definition at line 70 of file sam3_twi.h.

#define TWI_RHR_OFF 0x030

I2C registers base.

TWI register offsets.

Definition at line 67 of file sam3_twi.h.

#define TWI_RNCR_OFF 0x114

I2C registers base.

TWI register offsets.

Definition at line 74 of file sam3_twi.h.

#define TWI_RNPR_OFF 0x110

I2C registers base.

TWI register offsets.

Definition at line 73 of file sam3_twi.h.

#define TWI_RPR_OFF 0x100

I2C registers base.

TWI register offsets.

Definition at line 69 of file sam3_twi.h.

#define TWI_SMR_OFF 0x008

I2C registers base.

TWI register offsets.

Definition at line 60 of file sam3_twi.h.

#define TWI_SR_OFF 0x020

I2C registers base.

TWI register offsets.

Definition at line 63 of file sam3_twi.h.

#define TWI_TCR_OFF 0x10C

I2C registers base.

TWI register offsets.

Definition at line 72 of file sam3_twi.h.

#define TWI_THR_OFF 0x034

I2C registers base.

TWI register offsets.

Definition at line 68 of file sam3_twi.h.

#define TWI_TNCR_OFF 0x11C

I2C registers base.

TWI register offsets.

Definition at line 76 of file sam3_twi.h.

#define TWI_TNPR_OFF 0x118

I2C registers base.

TWI register offsets.

Definition at line 75 of file sam3_twi.h.

#define TWI_TPR_OFF 0x108

I2C registers base.

TWI register offsets.

Definition at line 71 of file sam3_twi.h.

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Defines

Detailed Description

Define Documentation