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sam3_twi.h
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00001 00036 #ifndef SAM3_TWI_H 00037 #define SAM3_TWI_H 00038 00040 #if CPU_CM3_SAM3X 00041 #define TWI0_BASE 0x4008C000 00042 #define TWI1_BASE 0x40090000 00043 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S 00044 #define TWI0_BASE 0x40018000 00045 #define TWI1_BASE 0x4001C000 00046 #elif CPU_CM3_SAM3U 00047 #define TWI0_BASE 0x40084000 00048 #define TWI1_BASE 0x40088000 00049 #else 00050 #error TWI registers not defined for selected CPU 00051 #endif 00052 00053 00057 /*\{*/ 00058 #define TWI_CR_OFF 0x000 00059 #define TWI_MMR_OFF 0x004 00060 #define TWI_SMR_OFF 0x008 00061 #define TWI_IADR_OFF 0x00C 00062 #define TWI_CWGR_OFF 0x010 00063 #define TWI_SR_OFF 0x020 00064 #define TWI_IER_OFF 0x024 00065 #define TWI_IDR_OFF 0x028 00066 #define TWI_IMR_OFF 0x02C 00067 #define TWI_RHR_OFF 0x030 00068 #define TWI_THR_OFF 0x034 00069 #define TWI_RPR_OFF 0x100 00070 #define TWI_RCR_OFF 0x104 00071 #define TWI_TPR_OFF 0x108 00072 #define TWI_TCR_OFF 0x10C 00073 #define TWI_RNPR_OFF 0x110 00074 #define TWI_RNCR_OFF 0x114 00075 #define TWI_TNPR_OFF 0x118 00076 #define TWI_TNCR_OFF 0x11C 00077 #define TWI_PTCR_OFF 0x120 00078 #define TWI_PTSR_OFF 0x124 00079 /*\}*/ 00080 00084 /*\{*/ 00085 #ifdef TWI_BASE 00086 #define TWI_CR (HWREG(TWI_BASE + TWI_CR_OFF)) 00087 #define TWI_MMR (HWREG(TWI_BASE + TWI_MMR_OFF)) 00088 #define TWI_SMR (HWREG(TWI_BASE + TWI_SMR_OFF)) 00089 #define TWI_IADR (HWREG(TWI_BASE + TWI_IADR_OFF)) 00090 #define TWI_CWGR (HWREG(TWI_BASE + TWI_CWGR_OFF)) 00091 #define TWI_SR (HWREG(TWI_BASE + TWI_SR_OFF)) 00092 #define TWI_IER (HWREG(TWI_BASE + TWI_IER_OFF)) 00093 #define TWI_IDR (HWREG(TWI_BASE + TWI_IDR_OFF)) 00094 #define TWI_IMR (HWREG(TWI_BASE + TWI_IMR_OFF)) 00095 #define TWI_RHR (HWREG(TWI_BASE + TWI_RHR_OFF)) 00096 #define TWI_THR (HWREG(TWI_BASE + TWI_THR_OFF)) 00097 #define TWI_RPR (HWREG(TWI_BASE + TWI_RPR_OFF)) 00098 #define TWI_RCR (HWREG(TWI_BASE + TWI_RCR_OFF)) 00099 #define TWI_TPR (HWREG(TWI_BASE + TWI_TPR_OFF)) 00100 #define TWI_TCR (HWREG(TWI_BASE + TWI_TCR_OFF)) 00101 #define TWI_RNPR (HWREG(TWI_BASE + TWI_RNPR_OFF)) 00102 #define TWI_RNCR (HWREG(TWI_BASE + TWI_RNCR_OFF)) 00103 #define TWI_TNPR (HWREG(TWI_BASE + TWI_TNPR_OFF)) 00104 #define TWI_TNCR (HWREG(TWI_BASE + TWI_TNCR_OFF)) 00105 #define TWI_PTCR (HWREG(TWI_BASE + TWI_PTCR_OFF)) 00106 #define TWI_PTSR (HWREG(TWI_BASE + TWI_PTSR_OFF)) 00107 #endif // TWI_BASE 00108 00109 #ifdef TWI0_BASE 00110 #define TWI0_CR (HWREG(TWI0_BASE + TWI_CR_OFF)) 00111 #define TWI0_MMR (HWREG(TWI0_BASE + TWI_MMR_OFF)) 00112 #define TWI0_SMR (HWREG(TWI0_BASE + TWI_SMR_OFF)) 00113 #define TWI0_IADR (HWREG(TWI0_BASE + TWI_IADR_OFF)) 00114 #define TWI0_CWGR (HWREG(TWI0_BASE + TWI_CWGR_OFF)) 00115 #define TWI0_SR (HWREG(TWI0_BASE + TWI_SR_OFF)) 00116 #define TWI0_IER (HWREG(TWI0_BASE + TWI_IER_OFF)) 00117 #define TWI0_IDR (HWREG(TWI0_BASE + TWI_IDR_OFF)) 00118 #define TWI0_IMR (HWREG(TWI0_BASE + TWI_IMR_OFF)) 00119 #define TWI0_RHR (HWREG(TWI0_BASE + TWI_RHR_OFF)) 00120 #define TWI0_THR (HWREG(TWI0_BASE + TWI_THR_OFF)) 00121 #define TWI0_RPR (HWREG(TWI0_BASE + TWI_RPR_OFF)) 00122 #define TWI0_RCR (HWREG(TWI0_BASE + TWI_RCR_OFF)) 00123 #define TWI0_TPR (HWREG(TWI0_BASE + TWI_TPR_OFF)) 00124 #define TWI0_TCR (HWREG(TWI0_BASE + TWI_TCR_OFF)) 00125 #define TWI0_RNPR (HWREG(TWI0_BASE + TWI_RNPR_OFF)) 00126 #define TWI0_RNCR (HWREG(TWI0_BASE + TWI_RNCR_OFF)) 00127 #define TWI0_TNPR (HWREG(TWI0_BASE + TWI_TNPR_OFF)) 00128 #define TWI0_TNCR (HWREG(TWI0_BASE + TWI_TNCR_OFF)) 00129 #define TWI0_PTCR (HWREG(TWI0_BASE + TWI_PTCR_OFF)) 00130 #define TWI0_PTSR (HWREG(TWI0_BASE + TWI_PTSR_OFF)) 00131 #endif // TWI0_BASE 00132 00133 #ifdef TWI1_BASE 00134 #define TWI1_CR (HWREG(TWI1_BASE + TWI_CR_OFF)) 00135 #define TWI1_MMR (HWREG(TWI1_BASE + TWI_MMR_OFF)) 00136 #define TWI1_SMR (HWREG(TWI1_BASE + TWI_SMR_OFF)) 00137 #define TWI1_IADR (HWREG(TWI1_BASE + TWI_IADR_OFF)) 00138 #define TWI1_CWGR (HWREG(TWI1_BASE + TWI_CWGR_OFF)) 00139 #define TWI1_SR (HWREG(TWI1_BASE + TWI_SR_OFF)) 00140 #define TWI1_IER (HWREG(TWI1_BASE + TWI_IER_OFF)) 00141 #define TWI1_IDR (HWREG(TWI1_BASE + TWI_IDR_OFF)) 00142 #define TWI1_IMR (HWREG(TWI1_BASE + TWI_IMR_OFF)) 00143 #define TWI1_RHR (HWREG(TWI1_BASE + TWI_RHR_OFF)) 00144 #define TWI1_THR (HWREG(TWI1_BASE + TWI_THR_OFF)) 00145 #define TWI1_RPR (HWREG(TWI1_BASE + TWI_RPR_OFF)) 00146 #define TWI1_RCR (HWREG(TWI1_BASE + TWI_RCR_OFF)) 00147 #define TWI1_TPR (HWREG(TWI1_BASE + TWI_TPR_OFF)) 00148 #define TWI1_TCR (HWREG(TWI1_BASE + TWI_TCR_OFF)) 00149 #define TWI1_RNPR (HWREG(TWI1_BASE + TWI_RNPR_OFF)) 00150 #define TWI1_RNCR (HWREG(TWI1_BASE + TWI_RNCR_OFF)) 00151 #define TWI1_TNPR (HWREG(TWI1_BASE + TWI_TNPR_OFF)) 00152 #define TWI1_TNCR (HWREG(TWI1_BASE + TWI_TNCR_OFF)) 00153 #define TWI1_PTCR (HWREG(TWI1_BASE + TWI_PTCR_OFF)) 00154 #define TWI1_PTSR (HWREG(TWI1_BASE + TWI_PTSR_OFF)) 00155 #endif // TWI1_BASE 00156 /*\}*/ 00157 00158 00162 /*\{*/ 00163 #define TWI_CR_START BV(0) 00164 #define TWI_CR_STOP BV(1) 00165 #define TWI_CR_MSEN BV(2) 00166 #define TWI_CR_MSDIS BV(3) 00167 #define TWI_CR_SVEN BV(4) 00168 #define TWI_CR_SVDIS BV(5) 00169 #define TWI_CR_QUICK BV(6) 00170 #define TWI_CR_SWRST BV(7) 00171 /*\}*/ 00172 00176 /*\{*/ 00177 #define TWI_MMR_IADRSZ_SHIFT 8 00178 #define TWI_MMR_IADRSZ_MASK (0x3 << TWI_MMR_IADRSZ_SHIFT) 00179 #define TWI_MMR_IADRSZ_NONE (0x0 << 8) 00180 #define TWI_MMR_IADRSZ_1_BYTE BV(8) 00181 #define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) 00182 #define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) 00183 #define TWI_MMR_MREAD BV(12) 00184 #define TWI_MMR_DADR_SHIFT 16 00185 #define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT) 00186 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_MASK & ((value) << TWI_MMR_DADR_SHIFT))) 00187 /*\}*/ 00188 00192 /*\{*/ 00193 #define TWI_SMR_SADR_SHIFT 16 00194 #define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT) 00195 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_MASK & ((value) << TWI_SMR_SADR_SHIFT))) 00196 /*\}*/ 00197 00201 /*\{*/ 00202 #define TWI_IADR_IADR_SHIFT 0 00203 #define TWI_IADR_IADR_MASK (0xffffff << TWI_IADR_IADR_SHIFT) 00204 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_MASK & ((value) << TWI_IADR_IADR_SHIFT))) 00205 /*\}*/ 00206 00210 /*\{*/ 00211 #define TWI_CWGR_CLDIV_SHIFT 0 00212 #define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) 00213 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_MASK & ((value) << TWI_CWGR_CLDIV_SHIFT))) 00214 #define TWI_CWGR_CHDIV_SHIFT 8 00215 #define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CHDIV_SHIFT) 00216 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_MASK & ((value) << TWI_CWGR_CHDIV_SHIFT))) 00217 #define TWI_CWGR_CKDIV_SHIFT 16 00218 #define TWI_CWGR_CKDIV_MASK (0x7 << TWI_CWGR_CKDIV_SHIFT) 00219 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_MASK & ((value) << TWI_CWGR_CKDIV_SHIFT))) 00220 /*\}*/ 00221 00225 /*\{*/ 00226 #define TWI_SR_TXCOMP BV(0) 00227 #define TWI_SR_RXRDY BV(1) 00228 #define TWI_SR_TXRDY BV(2) 00229 #define TWI_SR_SVREAD BV(3) 00230 #define TWI_SR_SVACC BV(4) 00231 #define TWI_SR_GACC BV(5) 00232 #define TWI_SR_OVRE BV(6) 00233 #define TWI_SR_NACK BV(8) 00234 #define TWI_SR_ARBLST BV(9) 00235 #define TWI_SR_SCLWS BV(10) 00236 #define TWI_SR_EOSACC BV(11) 00237 #define TWI_SR_ENDRX BV(12) 00238 #define TWI_SR_ENDTX BV(13) 00239 #define TWI_SR_RXBUFF BV(14) 00240 #define TWI_SR_TXBUFE BV(15) 00241 /*\}*/ 00242 00246 /*\{*/ 00247 #define TWI_IER_TXCOMP BV(0) 00248 #define TWI_IER_RXRDY BV(1) 00249 #define TWI_IER_TXRDY BV(2) 00250 #define TWI_IER_SVACC BV(4) 00251 #define TWI_IER_GACC BV(5) 00252 #define TWI_IER_OVRE BV(6) 00253 #define TWI_IER_NACK BV(8) 00254 #define TWI_IER_ARBLST BV(9) 00255 #define TWI_IER_SCL_WS BV(10) 00256 #define TWI_IER_EOSACC BV(11) 00257 #define TWI_IER_ENDRX BV(12) 00258 #define TWI_IER_ENDTX BV(13) 00259 #define TWI_IER_RXBUFF BV(14) 00260 #define TWI_IER_TXBUFE BV(15) 00261 /*\}*/ 00262 00266 /*\{*/ 00267 #define TWI_IDR_TXCOMP BV(0) 00268 #define TWI_IDR_RXRDY BV(1) 00269 #define TWI_IDR_TXRDY BV(2) 00270 #define TWI_IDR_SVACC BV(4) 00271 #define TWI_IDR_GACC BV(5) 00272 #define TWI_IDR_OVRE BV(6) 00273 #define TWI_IDR_NACK BV(8) 00274 #define TWI_IDR_ARBLST BV(9) 00275 #define TWI_IDR_SCL_WS BV(10) 00276 #define TWI_IDR_EOSACC BV(11) 00277 #define TWI_IDR_ENDRX BV(12) 00278 #define TWI_IDR_ENDTX BV(13) 00279 #define TWI_IDR_RXBUFF BV(14) 00280 #define TWI_IDR_TXBUFE BV(15) 00281 /*\}*/ 00282 00286 /*\{*/ 00287 #define TWI_IMR_TXCOMP BV(0) 00288 #define TWI_IMR_RXRDY BV(1) 00289 #define TWI_IMR_TXRDY BV(2) 00290 #define TWI_IMR_SVACC BV(4) 00291 #define TWI_IMR_GACC BV(5) 00292 #define TWI_IMR_OVRE BV(6) 00293 #define TWI_IMR_NACK BV(8) 00294 #define TWI_IMR_ARBLST BV(9) 00295 #define TWI_IMR_SCL_WS BV(10) 00296 #define TWI_IMR_EOSACC BV(11) 00297 #define TWI_IMR_ENDRX BV(12) 00298 #define TWI_IMR_ENDTX BV(13) 00299 #define TWI_IMR_RXBUFF BV(14) 00300 #define TWI_IMR_TXBUFE BV(15) 00301 /*\}*/ 00302 00306 /*\{*/ 00307 #define TWI_RHR_RXDATA_SHIFT 0 00308 #define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT) 00309 /*\}*/ 00310 00314 /*\{*/ 00315 #define TWI_THR_TXDATA_SHIFT 0 00316 #define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) 00317 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_MASK & ((value) << TWI_THR_TXDATA_SHIFT))) 00318 /*\}*/ 00319 00323 /*\{*/ 00324 #define TWI_RPR_RXPTR_SHIFT 0 00325 #define TWI_RPR_RXPTR_MASK (0xffffffff << TWI_RPR_RXPTR_SHIFT) 00326 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_MASK & ((value) << TWI_RPR_RXPTR_SHIFT))) 00327 /*\}*/ 00328 00332 /*\{*/ 00333 #define TWI_RCR_RXCTR_SHIFT 0 00334 #define TWI_RCR_RXCTR_MASK (0xffff << TWI_RCR_RXCTR_SHIFT) 00335 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_MASK & ((value) << TWI_RCR_RXCTR_SHIFT))) 00336 /*\}*/ 00337 00341 /*\{*/ 00342 #define TWI_TPR_TXPTR_SHIFT 0 00343 #define TWI_TPR_TXPTR_MASK (0xffffffff << TWI_TPR_TXPTR_SHIFT) 00344 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_MASK & ((value) << TWI_TPR_TXPTR_SHIFT))) 00345 /*\}*/ 00346 00350 /*\{*/ 00351 #define TWI_TCR_TXCTR_SHIFT 0 00352 #define TWI_TCR_TXCTR_MASK (0xffff << TWI_TCR_TXCTR_SHIFT) 00353 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_MASK & ((value) << TWI_TCR_TXCTR_SHIFT))) 00354 /*\}*/ 00355 00359 /*\{*/ 00360 #define TWI_RNPR_RXNPTR_SHIFT 0 00361 #define TWI_RNPR_RXNPTR_MASK (0xffffffff << TWI_RNPR_RXNPTR_SHIFT) 00362 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_MASK & ((value) << TWI_RNPR_RXNPTR_SHIFT))) 00363 /*\}*/ 00364 00368 /*\{*/ 00369 #define TWI_RNCR_RXNCTR_SHIFT 0 00370 #define TWI_RNCR_RXNCTR_MASK (0xffff << TWI_RNCR_RXNCTR_SHIFT) 00371 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_MASK & ((value) << TWI_RNCR_RXNCTR_SHIFT))) 00372 /*\}*/ 00373 00377 /*\{*/ 00378 #define TWI_TNPR_TXNPTR_SHIFT 0 00379 #define TWI_TNPR_TXNPTR_MASK (0xffffffff << TWI_TNPR_TXNPTR_SHIFT) 00380 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_MASK & ((value) << TWI_TNPR_TXNPTR_SHIFT))) 00381 /*\}*/ 00382 00386 /*\{*/ 00387 #define TWI_TNCR_TXNCTR_SHIFT 0 00388 #define TWI_TNCR_TXNCTR_MASK (0xffff << TWI_TNCR_TXNCTR_SHIFT) 00389 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_MASK & ((value) << TWI_TNCR_TXNCTR_SHIFT))) 00390 /*\}*/ 00391 00395 /*\{*/ 00396 #define TWI_PTCR_RXTEN BV(0) 00397 #define TWI_PTCR_RXTDIS BV(1) 00398 #define TWI_PTCR_TXTEN BV(8) 00399 #define TWI_PTCR_TXTDIS BV(9) 00400 /*\}*/ 00401 00405 /*\{*/ 00406 #define TWI_PTSR_RXTEN BV(0) 00407 #define TWI_PTSR_TXTEN BV(8) 00408 /*\}*/ 00409 00410 #endif /* SAM3_TWI_H */
