00001
00041 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
00042 #include <hw/hw_cpufreq.h>  /* CPU_FREQ */
00043
00044 #include "cfg/cfg_ser.h"
00045
00046 #include <cfg/macros.h> /* DIV_ROUND */
00047 #include <cfg/debug.h>
00048 #include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
00049
00050 #include <drv/ser.h>
00051 #include <drv/ser_p.h>
00052 #include <drv/timer.h>
00053
00054 #include <struct/fifobuf.h>
00055
00056 #include <avr/io.h>
00057
00058 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
00059     #include <avr/interrupt.h>
00060 #else
00061     #include <avr/signal.h>
00062 #endif
00063 
00064
00065 #if !CONFIG_SER_HWHANDSHAKE
00066 
00070     #define RTS_ON      do {} while (0)
00071     #define RTS_OFF     do {} while (0)
00072     #define IS_CTS_ON   true
00073     #define EIMSKF_CTS  0 
00074     /*\}*/
00075 #endif
00076 
00077 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 \
00078     || CPU_AVR_ATMEGA324P || CPU_AVR_ATMEGA644P
00079     #define BIT_RXCIE0 RXCIE0
00080     #define BIT_RXEN0  RXEN0
00081     #define BIT_TXEN0  TXEN0
00082     #define BIT_UDRIE0 UDRIE0
00083 
00084     #define BIT_RXCIE1 RXCIE1
00085     #define BIT_RXEN1  RXEN1
00086     #define BIT_TXEN1  TXEN1
00087     #define BIT_UDRIE1 UDRIE1
00088     #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00089         #define BIT_RXCIE2 RXCIE2
00090         #define BIT_RXEN2  RXEN2
00091         #define BIT_TXEN2  TXEN2
00092         #define BIT_UDRIE2 UDRIE2
00093 
00094         #define BIT_RXCIE3 RXCIE3
00095         #define BIT_RXEN3  RXEN3
00096         #define BIT_TXEN3  TXEN3
00097         #define BIT_UDRIE3 UDRIE3
00098     #endif
00099 #elif CPU_AVR_ATMEGA88P || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
00100     #define BIT_RXCIE0 RXCIE0
00101     #define BIT_RXEN0  RXEN0
00102     #define BIT_TXEN0  TXEN0
00103     #define BIT_UDRIE0 UDRIE0
00104 
00105     #define BIT_RXCIE1 RXCIE0
00106     #define BIT_RXEN1  RXEN0
00107     #define BIT_TXEN1  TXEN0
00108     #define BIT_UDRIE1 UDRIE0
00109 #else
00110     #define BIT_RXCIE0 RXCIE
00111     #define BIT_RXEN0  RXEN
00112     #define BIT_TXEN0  TXEN
00113     #define BIT_UDRIE0 UDRIE
00114 
00115     #define BIT_RXCIE1 RXCIE
00116     #define BIT_RXEN1  RXEN
00117     #define BIT_TXEN1  TXEN
00118     #define BIT_UDRIE1 UDRIE
00119 #endif
00120 
00121
00142 #ifndef SER_UART0_BUS_TXINIT
00143 
00149     #define SER_UART0_BUS_TXINIT do { \
00150         UCSR0A = 0; /* The Arduino Uno bootloader turns on U2X0 */ \
00151         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00152     } while (0)
00153 #endif
00154 
00155 #ifndef SER_UART0_BUS_TXBEGIN
00156 
00162     #define SER_UART0_BUS_TXBEGIN do { \
00163         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00164     } while (0)
00165 #endif
00166 
00167 #ifndef SER_UART0_BUS_TXCHAR
00168 
00171     #define SER_UART0_BUS_TXCHAR(c) do { \
00172         UDR0 = (c); \
00173     } while (0)
00174 #endif
00175 
00176 #ifndef SER_UART0_BUS_TXEND
00177 
00184     #define SER_UART0_BUS_TXEND do { \
00185         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00186     } while (0)
00187 #endif
00188 
00189 #ifndef SER_UART0_BUS_TXOFF
00190 
00197     #ifdef __doxygen__
00198     #define SER_UART0_BUS_TXOFF
00199     #endif
00200 #endif
00201 
00202 #ifndef SER_UART1_BUS_TXINIT
00203 
00204     #define SER_UART1_BUS_TXINIT do { \
00205         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00206     } while (0)
00207 #endif
00208 #ifndef SER_UART1_BUS_TXBEGIN
00209 
00210     #define SER_UART1_BUS_TXBEGIN do { \
00211         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00212     } while (0)
00213 #endif
00214 #ifndef SER_UART1_BUS_TXCHAR
00215 
00216     #define SER_UART1_BUS_TXCHAR(c) do { \
00217         UDR1 = (c); \
00218     } while (0)
00219 #endif
00220 #ifndef SER_UART1_BUS_TXEND
00221 
00222     #define SER_UART1_BUS_TXEND do { \
00223         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00224     } while (0)
00225 #endif
00226 #ifndef SER_UART1_BUS_TXOFF
00227 
00232     #ifdef __doxygen__
00233     #define SER_UART1_BUS_TXOFF
00234     #endif
00235 #endif
00236 
00237 #ifndef SER_UART2_BUS_TXINIT
00238 
00239     #define SER_UART2_BUS_TXINIT do { \
00240         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00241     } while (0)
00242 #endif
00243 #ifndef SER_UART2_BUS_TXBEGIN
00244 
00245     #define SER_UART2_BUS_TXBEGIN do { \
00246         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00247     } while (0)
00248 #endif
00249 #ifndef SER_UART2_BUS_TXCHAR
00250 
00251     #define SER_UART2_BUS_TXCHAR(c) do { \
00252         UDR2 = (c); \
00253     } while (0)
00254 #endif
00255 #ifndef SER_UART2_BUS_TXEND
00256 
00257     #define SER_UART2_BUS_TXEND do { \
00258         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00259     } while (0)
00260 #endif
00261 #ifndef SER_UART2_BUS_TXOFF
00262 
00267     #ifdef __doxygen__
00268     #define SER_UART2_BUS_TXOFF
00269     #endif
00270 #endif
00271 
00272 #ifndef SER_UART3_BUS_TXINIT
00273 
00274     #define SER_UART3_BUS_TXINIT do { \
00275         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00276     } while (0)
00277 #endif
00278 #ifndef SER_UART3_BUS_TXBEGIN
00279 
00280     #define SER_UART3_BUS_TXBEGIN do { \
00281         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00282     } while (0)
00283 #endif
00284 #ifndef SER_UART3_BUS_TXCHAR
00285 
00286     #define SER_UART3_BUS_TXCHAR(c) do { \
00287         UDR3 = (c); \
00288     } while (0)
00289 #endif
00290 #ifndef SER_UART3_BUS_TXEND
00291 
00292     #define SER_UART3_BUS_TXEND do { \
00293         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00294     } while (0)
00295 #endif
00296 #ifndef SER_UART3_BUS_TXOFF
00297 
00302     #ifdef __doxygen__
00303     #define SER_UART3_BUS_TXOFF
00304     #endif
00305 #endif
00306 /*\}*/
00307
00308
00317 #ifndef SER_SPI_BUS_TXINIT
00318 
00322     #define SER_SPI_BUS_TXINIT
00323 #endif
00324 
00325 #ifndef SER_SPI_BUS_TXCLOSE
00326 
00330     #define SER_SPI_BUS_TXCLOSE
00331 #endif
00332 /*\}*/
00333
00334
00335 /* SPI port and pin configuration */
00336 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
00337     || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00338     #define SPI_PORT      PORTB
00339     #define SPI_DDR       DDRB
00340     #define SPI_SS_BIT    PB0
00341     #define SPI_SCK_BIT   PB1
00342     #define SPI_MOSI_BIT  PB2
00343     #define SPI_MISO_BIT  PB3
00344 // TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
00345 // They should be the same!
00346 #elif CPU_AVR_ATMEGA328P
00347     #define SPI_PORT      PORTB
00348     #define SPI_DDR       DDRB
00349     #define SPI_SS_BIT    PORTB2
00350     #define SPI_SCK_BIT   PORTB5
00351     #define SPI_MOSI_BIT  PORTB3
00352     #define SPI_MISO_BIT  PORTB4
00353 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA88P || CPU_AVR_ATMEGA168
00354     #define SPI_PORT      PORTB
00355     #define SPI_DDR       DDRB
00356     #define SPI_SS_BIT    PB2
00357     #define SPI_SCK_BIT   PB5
00358     #define SPI_MOSI_BIT  PB3
00359     #define SPI_MISO_BIT  PB4
00360 #elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA324P || CPU_AVR_ATMEGA644P
00361     #define SPI_PORT      PORTB
00362     #define SPI_DDR       DDRB
00363     #define SPI_SS_BIT    PB4
00364     #define SPI_SCK_BIT   PB7
00365     #define SPI_MOSI_BIT  PB5
00366     #define SPI_MISO_BIT  PB6
00367 #else
00368     #error Unknown architecture
00369 #endif
00370 
00371 /* USART register definitions */
00372 #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00373     #define AVR_HAS_UART1 1
00374     #define AVR_HAS_UART2 1
00375     #define AVR_HAS_UART3 1
00376 #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 \
00377     || CPU_AVR_ATMEGA324P || CPU_AVR_ATMEGA644P
00378     #define AVR_HAS_UART1 1
00379     #define AVR_HAS_UART2 0
00380     #define AVR_HAS_UART3 0
00381 #elif CPU_AVR_ATMEGA88P || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
00382     #define AVR_HAS_UART1 0
00383     #define AVR_HAS_UART2 0
00384     #define AVR_HAS_UART3 0
00385     #define USART0_UDRE_vect USART_UDRE_vect
00386     #define USART0_RX_vect USART_RX_vect
00387     #define USART0_TX_vect USART_TX_vect
00388 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
00389     #define AVR_HAS_UART1 0
00390     #define AVR_HAS_UART2 0
00391     #define AVR_HAS_UART3 0
00392     #define UCSR0A UCSRA
00393     #define UCSR0B UCSRB
00394     #define UCSR0C UCSRC
00395     #define UDR0   UDR
00396     #define UBRR0L UBRRL
00397     #define UBRR0H UBRRH
00398     #define UPM01  UPM1
00399     #define UPM00  UPM0
00400     #define USART0_UDRE_vect USART_UDRE_vect
00401     #define USART0_RX_vect USART_RXC_vect
00402     #define USART0_TX_vect USART_TXC_vect
00403 #elif CPU_AVR_ATMEGA103
00404     #define AVR_HAS_UART1 0
00405     #define AVR_HAS_UART2 0
00406     #define AVR_HAS_UART3 0
00407     #define UCSR0B UCR
00408     #define UDR0   UDR
00409     #define UCSR0A USR
00410     #define UBRR0L UBRR
00411     #define USART0_UDRE_vect USART_UDRE_vect
00412     #define USART0_RX_vect USART_RX_vect
00413     #define USART0_TX_vect USART_TX_vect
00414 #else
00415     #error Unknown architecture
00416 #endif
00417 
00418
00419 /* From the high-level serial driver */
00420 extern struct Serial *ser_handles[SER_CNT];
00421
00422 /* TX and RX buffers */
00423 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
00424 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
00425 #if AVR_HAS_UART1
00426     static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
00427     static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
00428 #endif
00429 #if AVR_HAS_UART2
00430     static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
00431     static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
00432 #endif
00433 #if AVR_HAS_UART3
00434     static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
00435     static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
00436 #endif
00437 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
00438 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
00439
00440
00457 struct AvrSerial
00458 {
00459     struct SerialHardware hw;
00460     volatile bool sending;
00461 };
00462
00463 static uint16_t uart_period(unsigned long bps)
00464 {
00465     uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, bps) - 1;
00466
00467     #ifdef _DEBUG
00468         long skew = bps - ((CPU_FREQ / 16UL) / (long)(period + 1));
00469         /* 8N1 is reliable within 3% skew */
00470         if ((unsigned long)ABS(skew) > bps / (100 / 3))
00471             kprintf("Baudrate off by %ldbps\n", skew);
00472     #endif
00473 
00474     //DB(kprintf("uart_period(bps=%lu): period=%u\n", bps, period);)
00475     return period;
00476 }
00477
00478 /*
00479  * Callbacks
00480  */
00481 static void uart0_init(
00482     UNUSED_ARG(struct SerialHardware *, _hw),
00483     UNUSED_ARG(struct Serial *, ser))
00484 {
00485     SER_UART0_BUS_TXINIT;
00486     RTS_ON;
00487     SER_STROBE_INIT;
00488 }
00489
00490 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00491 {
00492     UCSR0B = 0;
00493 }
00494
00495 static void uart0_enabletxirq(struct SerialHardware *_hw)
00496 {
00497     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00498
00499     /*
00500      * WARNING: racy code here!  The tx interrupt sets hw->sending to false
00501      * when it runs with an empty fifo.  The order of statements in the
00502      * if-block matters.
00503      */
00504     if (!hw->sending)
00505     {
00506         hw->sending = true;
00507         SER_UART0_BUS_TXBEGIN;
00508     }
00509 }
00510
00511 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00512 {
00513     uint16_t period = uart_period(rate);
00514
00515 #if !CPU_AVR_ATMEGA103
00516     UBRR0H = period >> 8;
00517 #endif
00518     UBRR0L = period;
00519 }
00520
00521 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00522 {
00523 #if !CPU_AVR_ATMEGA103
00524     UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
00525 #endif
00526 }
00527
00528 #if AVR_HAS_UART1
00529 
00530 static void uart1_init(
00531     UNUSED_ARG(struct SerialHardware *, _hw),
00532     UNUSED_ARG(struct Serial *, ser))
00533 {
00534     SER_UART1_BUS_TXINIT;
00535     RTS_ON;
00536     SER_STROBE_INIT;
00537 }
00538
00539 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00540 {
00541     UCSR1B = 0;
00542 }
00543
00544 static void uart1_enabletxirq(struct SerialHardware *_hw)
00545 {
00546     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00547
00548     /*
00549      * WARNING: racy code here!  The tx interrupt
00550      * sets hw->sending to false when it runs with
00551      * an empty fifo.  The order of the statements
00552      * in the if-block matters.
00553      */
00554     if (!hw->sending)
00555     {
00556         hw->sending = true;
00557         SER_UART1_BUS_TXBEGIN;
00558     }
00559 }
00560
00561 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00562 {
00563     uint16_t period = uart_period(rate);
00564     UBRR1H = period >> 8;
00565     UBRR1L = period;
00566 }
00567
00568 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00569 {
00570     UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
00571 }
00572
00573 #endif // AVR_HAS_UART1
00574 
00575 #if AVR_HAS_UART2
00576 
00577 static void uart2_init(
00578     UNUSED_ARG(struct SerialHardware *, _hw),
00579     UNUSED_ARG(struct Serial *, ser))
00580 {
00581     SER_UART2_BUS_TXINIT;
00582     RTS_ON;
00583     SER_STROBE_INIT;
00584 }
00585
00586 static void uart2_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00587 {
00588     UCSR2B = 0;
00589 }
00590
00591 static void uart2_enabletxirq(struct SerialHardware *_hw)
00592 {
00593     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00594
00595     /*
00596      * WARNING: racy code here!  The tx interrupt
00597      * sets hw->sending to false when it runs with
00598      * an empty fifo.  The order of the statements
00599      * in the if-block matters.
00600      */
00601     if (!hw->sending)
00602     {
00603         hw->sending = true;
00604         SER_UART2_BUS_TXBEGIN;
00605     }
00606 }
00607
00608 static void uart2_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00609 {
00610     uint16_t period = uart_period(rate);
00611     UBRR2H = period >> 8;
00612     UBRR2L = period;
00613 }
00614
00615 static void uart2_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00616 {
00617     UCSR2C = (UCSR2C & ~(BV(UPM21) | BV(UPM20))) | ((parity) << UPM20);
00618 }
00619
00620 #endif // AVR_HAS_UART2
00621 
00622 #if AVR_HAS_UART3
00623 
00624 static void uart3_init(
00625     UNUSED_ARG(struct SerialHardware *, _hw),
00626     UNUSED_ARG(struct Serial *, ser))
00627 {
00628     SER_UART3_BUS_TXINIT;
00629     RTS_ON;
00630     SER_STROBE_INIT;
00631 }
00632
00633 static void uart3_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00634 {
00635     UCSR3B = 0;
00636 }
00637
00638 static void uart3_enabletxirq(struct SerialHardware *_hw)
00639 {
00640     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00641
00642     /*
00643      * WARNING: racy code here!  The tx interrupt
00644      * sets hw->sending to false when it runs with
00645      * an empty fifo.  The order of the statements
00646      * in the if-block matters.
00647      */
00648     if (!hw->sending)
00649     {
00650         hw->sending = true;
00651         SER_UART3_BUS_TXBEGIN;
00652     }
00653 }
00654
00655 static void uart3_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00656 {
00657     uint16_t period = uart_period(rate);
00658     UBRR3H = period >> 8;
00659     UBRR3L = period;
00660 }
00661
00662 static void uart3_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00663 {
00664     UCSR3C = (UCSR3C & ~(BV(UPM31) | BV(UPM30))) | ((parity) << UPM30);
00665 }
00666
00667 #endif // AVR_HAS_UART3
00668 
00669
00670 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
00671 {
00672     /*
00673      * Set MOSI and SCK ports out, MISO in.
00674      *
00675      * The ATmega64/128 datasheet explicitly states that the input/output
00676      * state of the SPI pins is not significant, as when the SPI is
00677      * active the I/O port are overrided.
00678      * This is *blatantly FALSE*.
00679      *
00680      * Moreover, the MISO pin on the board_kc *must* be in high impedance
00681      * state even when the SPI is off, because the line is wired together
00682      * with the KBus serial RX, and the transmitter of the slave boards
00683      * would be unable to drive the line.
00684      */
00685     ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
00686
00687     /*
00688      * If the SPI master mode is activated and the SS pin is in input and tied low,
00689      * the SPI hardware will automatically switch to slave mode!
00690      * For proper communication this pins should therefore be:
00691      * - as output
00692      * - as input but tied high forever!
00693      * This driver set the pin as output.
00694      */
00695     #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
00696     ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
00697
00698     ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
00699     /* Enable SPI, IRQ on, Master */
00700     SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
00701
00702     /* Set data order */
00703     #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
00704         SPCR |= BV(DORD);
00705     #endif
00706 
00707     /* Set SPI clock rate */
00708     #if CONFIG_SPI_CLOCK_DIV == 128
00709         SPCR |= (BV(SPR1) | BV(SPR0));
00710     #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
00711         SPCR |= BV(SPR1);
00712     #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
00713         SPCR |= BV(SPR0);
00714     #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
00715         // SPR0 & SDPR1 both at 0
00716     #else
00717         #error Unsupported SPI clock division factor.
00718     #endif
00719 
00720     /* Set SPI2X bit (spi double frequency) */
00721     #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
00722       || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
00723         SPSR &= ~BV(SPI2X);
00724     #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
00725         SPSR |= BV(SPI2X);
00726     #else
00727         #error Unsupported SPI clock division factor.
00728     #endif
00729 
00730     /* Set clock polarity */
00731     #if CONFIG_SPI_CLOCK_POL == 1
00732         SPCR |= BV(CPOL);
00733     #endif
00734 
00735     /* Set clock phase */
00736     #if CONFIG_SPI_CLOCK_PHASE == 1
00737         SPCR |= BV(CPHA);
00738     #endif
00739     SER_SPI_BUS_TXINIT;
00740
00741     SER_STROBE_INIT;
00742 }
00743
00744 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00745 {
00746     SPCR = 0;
00747
00748     SER_SPI_BUS_TXCLOSE;
00749
00750     /* Set all pins as inputs */
00751     ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
00752 }
00753
00754 static void spi_starttx(struct SerialHardware *_hw)
00755 {
00756     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00757
00758     cpu_flags_t flags;
00759     IRQ_SAVE_DISABLE(flags);
00760
00761     /* Send data only if the SPI is not already transmitting */
00762     if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
00763     {
00764         hw->sending = true;
00765         SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
00766     }
00767
00768     IRQ_RESTORE(flags);
00769 }
00770
00771 static void spi_setbaudrate(
00772     UNUSED_ARG(struct SerialHardware *, _hw),
00773     UNUSED_ARG(unsigned long, rate))
00774 {
00775     // nop
00776 }
00777
00778 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
00779 {
00780     // nop
00781 }
00782
00783 static bool tx_sending(struct SerialHardware* _hw)
00784 {
00785     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00786     return hw->sending;
00787 }
00788
00789
00790
00791 // FIXME: move into compiler.h?  Ditch?
00792 #if COMPILER_C99
00793     #define C99INIT(name,val) .name = val
00794 #elif defined(__GNUC__)
00795     #define C99INIT(name,val) name: val
00796 #else
00797     #warning No designated initializers, double check your code
00798     #define C99INIT(name,val) (val)
00799 #endif
00800 
00801 /*
00802  * High-level interface data structures
00803  */
00804 static const struct SerialHardwareVT UART0_VT =
00805 {
00806     C99INIT(init, uart0_init),
00807     C99INIT(cleanup, uart0_cleanup),
00808     C99INIT(setBaudrate, uart0_setbaudrate),
00809     C99INIT(setParity, uart0_setparity),
00810     C99INIT(txStart, uart0_enabletxirq),
00811     C99INIT(txSending, tx_sending),
00812 };
00813
00814 #if AVR_HAS_UART1
00815 static const struct SerialHardwareVT UART1_VT =
00816 {
00817     C99INIT(init, uart1_init),
00818     C99INIT(cleanup, uart1_cleanup),
00819     C99INIT(setBaudrate, uart1_setbaudrate),
00820     C99INIT(setParity, uart1_setparity),
00821     C99INIT(txStart, uart1_enabletxirq),
00822     C99INIT(txSending, tx_sending),
00823 };
00824 #endif // AVR_HAS_UART1
00825 
00826 #if AVR_HAS_UART2
00827 static const struct SerialHardwareVT UART2_VT =
00828 {
00829     C99INIT(init, uart2_init),
00830     C99INIT(cleanup, uart2_cleanup),
00831     C99INIT(setBaudrate, uart2_setbaudrate),
00832     C99INIT(setParity, uart2_setparity),
00833     C99INIT(txStart, uart2_enabletxirq),
00834     C99INIT(txSending, tx_sending),
00835 };
00836 #endif // AVR_HAS_UART2
00837 
00838 #if AVR_HAS_UART3
00839 static const struct SerialHardwareVT UART3_VT =
00840 {
00841     C99INIT(init, uart3_init),
00842     C99INIT(cleanup, uart3_cleanup),
00843     C99INIT(setBaudrate, uart3_setbaudrate),
00844     C99INIT(setParity, uart3_setparity),
00845     C99INIT(txStart, uart3_enabletxirq),
00846     C99INIT(txSending, tx_sending),
00847 };
00848 #endif // AVR_HAS_UART3
00849 
00850 static const struct SerialHardwareVT SPI_VT =
00851 {
00852     C99INIT(init, spi_init),
00853     C99INIT(cleanup, spi_cleanup),
00854     C99INIT(setBaudrate, spi_setbaudrate),
00855     C99INIT(setParity, spi_setparity),
00856     C99INIT(txStart, spi_starttx),
00857     C99INIT(txSending, tx_sending),
00858 };
00859
00860 static struct AvrSerial UARTDescs[SER_CNT] =
00861 {
00862     {
00863         C99INIT(hw, ) {
00864             C99INIT(table, &UART0_VT),
00865             C99INIT(txbuffer, uart0_txbuffer),
00866             C99INIT(rxbuffer, uart0_rxbuffer),
00867             C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
00868             C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
00869         },
00870         C99INIT(sending, false),
00871     },
00872 #if AVR_HAS_UART1
00873     {
00874         C99INIT(hw, ) {
00875             C99INIT(table, &UART1_VT),
00876             C99INIT(txbuffer, uart1_txbuffer),
00877             C99INIT(rxbuffer, uart1_rxbuffer),
00878             C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
00879             C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
00880         },
00881         C99INIT(sending, false),
00882     },
00883 #endif
00884 #if AVR_HAS_UART2
00885     {
00886         C99INIT(hw, ) {
00887             C99INIT(table, &UART2_VT),
00888             C99INIT(txbuffer, uart2_txbuffer),
00889             C99INIT(rxbuffer, uart2_rxbuffer),
00890             C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
00891             C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
00892         },
00893         C99INIT(sending, false),
00894     },
00895 #endif
00896 #if AVR_HAS_UART3
00897     {
00898         C99INIT(hw, ) {
00899             C99INIT(table, &UART3_VT),
00900             C99INIT(txbuffer, uart3_txbuffer),
00901             C99INIT(rxbuffer, uart3_rxbuffer),
00902             C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
00903             C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
00904         },
00905         C99INIT(sending, false),
00906     },
00907 #endif
00908     {
00909         C99INIT(hw, ) {
00910             C99INIT(table, &SPI_VT),
00911             C99INIT(txbuffer, spi_txbuffer),
00912             C99INIT(rxbuffer, spi_rxbuffer),
00913             C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
00914             C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
00915         },
00916         C99INIT(sending, false),
00917     }
00918 };
00919
00920 struct SerialHardware *ser_hw_getdesc(int unit)
00921 {
00922     ASSERT(unit < SER_CNT);
00923     return &UARTDescs[unit].hw;
00924 }
00925
00926
00927 /*
00928  * Interrupt handlers
00929  */
00930
00931 #if CONFIG_SER_HWHANDSHAKE
00932 
00934 DECLARE_ISR(SIG_CTS)
00935 {
00936     // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
00937     UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
00938     EIMSK &= ~EIMSKF_CTS;
00939 }
00940
00941 #endif // CONFIG_SER_HWHANDSHAKE
00942 
00943
00947 DECLARE_ISR(USART0_UDRE_vect)
00948 {
00949     SER_STROBE_ON;
00950
00951     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
00952
00953     if (fifo_isempty(txfifo))
00954     {
00955         SER_UART0_BUS_TXEND;
00956 #ifndef SER_UART0_BUS_TXOFF
00957         UARTDescs[SER_UART0].sending = false;
00958 #endif
00959     }
00960 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
00961     else if (!IS_CTS_ON)
00962     {
00963         // Disable rx interrupt and tx, enable CTS interrupt
00964         // UNTESTED
00965         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
00966         EIFR |= EIMSKF_CTS;
00967         EIMSK |= EIMSKF_CTS;
00968     }
00969 #endif
00970     else
00971     {
00972         char c = fifo_pop(txfifo);
00973         SER_UART0_BUS_TXCHAR(c);
00974     }
00975
00976     SER_STROBE_OFF;
00977 }
00978
00979 #ifdef SER_UART0_BUS_TXOFF
00980 
00995 DECLARE_ISR(USART0_TX_vect)
00996 {
00997     SER_STROBE_ON;
00998
00999     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
01000     if (fifo_isempty(txfifo))
01001     {
01002         SER_UART0_BUS_TXOFF;
01003         UARTDescs[SER_UART0].sending = false;
01004     }
01005     else
01006         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
01007
01008     SER_STROBE_OFF;
01009 }
01010 #endif /* SER_UART0_BUS_TXOFF */
01011
01012
01013 #if AVR_HAS_UART1
01014 
01018 DECLARE_ISR(USART1_UDRE_vect)
01019 {
01020     SER_STROBE_ON;
01021
01022     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
01023
01024     if (fifo_isempty(txfifo))
01025     {
01026         SER_UART1_BUS_TXEND;
01027 #ifndef SER_UART1_BUS_TXOFF
01028         UARTDescs[SER_UART1].sending = false;
01029 #endif
01030     }
01031 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
01032     else if (!IS_CTS_ON)
01033     {
01034         // Disable rx interrupt and tx, enable CTS interrupt
01035         // UNTESTED
01036         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
01037         EIFR |= EIMSKF_CTS;
01038         EIMSK |= EIMSKF_CTS;
01039     }
01040 #endif
01041     else
01042     {
01043         char c = fifo_pop(txfifo);
01044         SER_UART1_BUS_TXCHAR(c);
01045     }
01046
01047     SER_STROBE_OFF;
01048 }
01049
01050 #ifdef SER_UART1_BUS_TXOFF
01051 
01056 DECLARE_ISR(USART1_TX_vect)
01057 {
01058     SER_STROBE_ON;
01059
01060     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
01061     if (fifo_isempty(txfifo))
01062     {
01063         SER_UART1_BUS_TXOFF;
01064         UARTDescs[SER_UART1].sending = false;
01065     }
01066     else
01067         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
01068
01069     SER_STROBE_OFF;
01070 }
01071 #endif /* SER_UART1_BUS_TXOFF */
01072
01073 #endif // AVR_HAS_UART1
01074 
01075 #if AVR_HAS_UART2
01076 
01080 DECLARE_ISR(USART2_UDRE_vect)
01081 {
01082     SER_STROBE_ON;
01083
01084     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
01085
01086     if (fifo_isempty(txfifo))
01087     {
01088         SER_UART2_BUS_TXEND;
01089 #ifndef SER_UART2_BUS_TXOFF
01090         UARTDescs[SER_UART2].sending = false;
01091 #endif
01092     }
01093     else
01094     {
01095         char c = fifo_pop(txfifo);
01096         SER_UART2_BUS_TXCHAR(c);
01097     }
01098
01099     SER_STROBE_OFF;
01100 }
01101
01102 #ifdef SER_UART2_BUS_TXOFF
01103 
01108 DECLARE_ISR(USART2_TX_vect)
01109 {
01110     SER_STROBE_ON;
01111
01112     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
01113     if (fifo_isempty(txfifo))
01114     {
01115         SER_UART2_BUS_TXOFF;
01116         UARTDescs[SER_UART2].sending = false;
01117     }
01118     else
01119         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2);
01120
01121     SER_STROBE_OFF;
01122 }
01123 #endif /* SER_UART2_BUS_TXOFF */
01124
01125 #endif // AVR_HAS_UART2
01126 
01127 #if AVR_HAS_UART3
01128 
01132 DECLARE_ISR(USART3_UDRE_vect)
01133 {
01134     SER_STROBE_ON;
01135
01136     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
01137
01138     if (fifo_isempty(txfifo))
01139     {
01140         SER_UART3_BUS_TXEND;
01141 #ifndef SER_UART3_BUS_TXOFF
01142         UARTDescs[SER_UART3].sending = false;
01143 #endif
01144     }
01145     else
01146     {
01147         char c = fifo_pop(txfifo);
01148         SER_UART3_BUS_TXCHAR(c);
01149     }
01150
01151     SER_STROBE_OFF;
01152 }
01153
01154 #ifdef SER_UART3_BUS_TXOFF
01155 
01160 DECLARE_ISR(USART3_TX_vect)
01161 {
01162     SER_STROBE_ON;
01163
01164     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
01165     if (fifo_isempty(txfifo))
01166     {
01167         SER_UART3_BUS_TXOFF;
01168         UARTDescs[SER_UART3].sending = false;
01169     }
01170     else
01171         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3);
01172
01173     SER_STROBE_OFF;
01174 }
01175 #endif /* SER_UART3_BUS_TXOFF */
01176
01177 #endif // AVR_HAS_UART3
01178 
01179
01195 DECLARE_ISR(USART0_RX_vect)
01196 {
01197     SER_STROBE_ON;
01198
01199     /* Disable Recv complete IRQ */
01200     //UCSR0B &= ~BV(RXCIE);
01201     //IRQ_ENABLE;
01202
01203     /* Should be read before UDR */
01204     ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01205
01206     /* To clear the RXC flag we must _always_ read the UDR even when we're
01207      * not going to accept the incoming data, otherwise a new interrupt
01208      * will occur once the handler terminates.
01209      */
01210     char c = UDR0;
01211     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
01212
01213     if (fifo_isfull(rxfifo))
01214         ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
01215     else
01216     {
01217         fifo_push(rxfifo, c);
01218 #if CONFIG_SER_HWHANDSHAKE
01219         if (fifo_isfull(rxfifo))
01220             RTS_OFF;
01221 #endif
01222     }
01223
01224     /* Reenable receive complete int */
01225     //IRQ_DISABLE;
01226     //UCSR0B |= BV(RXCIE);
01227
01228     SER_STROBE_OFF;
01229 }
01230
01231
01232 #if AVR_HAS_UART1
01233 
01245 DECLARE_ISR(USART1_RX_vect)
01246 {
01247     SER_STROBE_ON;
01248
01249     /* Disable Recv complete IRQ */
01250     //UCSR1B &= ~BV(RXCIE);
01251     //IRQ_ENABLE;
01252
01253     /* Should be read before UDR */
01254     ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01255
01256     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01257      * not going to accept the incoming data
01258      */
01259     char c = UDR1;
01260     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
01261     //ASSERT_VALID_FIFO(rxfifo);
01262
01263     if (UNLIKELY(fifo_isfull(rxfifo)))
01264         ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
01265     else
01266     {
01267         fifo_push(rxfifo, c);
01268 #if CONFIG_SER_HWHANDSHAKE
01269         if (fifo_isfull(rxfifo))
01270             RTS_OFF;
01271 #endif
01272     }
01273     /* Re-enable receive complete int */
01274     //IRQ_DISABLE;
01275     //UCSR1B |= BV(RXCIE);
01276
01277     SER_STROBE_OFF;
01278 }
01279
01280 #endif // AVR_HAS_UART1
01281 
01282 #if AVR_HAS_UART2
01283 
01295 DECLARE_ISR(USART2_RX_vect)
01296 {
01297     SER_STROBE_ON;
01298
01299     /* Disable Recv complete IRQ */
01300     //UCSR1B &= ~BV(RXCIE);
01301     //IRQ_ENABLE;
01302
01303     /* Should be read before UDR */
01304     ser_handles[SER_UART2]->status |= UCSR2A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01305
01306     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01307      * not going to accept the incoming data
01308      */
01309     char c = UDR2;
01310     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART2]->rxfifo;
01311     //ASSERT_VALID_FIFO(rxfifo);
01312
01313     if (UNLIKELY(fifo_isfull(rxfifo)))
01314         ser_handles[SER_UART2]->status |= SERRF_RXFIFOOVERRUN;
01315     else
01316     {
01317         fifo_push(rxfifo, c);
01318 #if CONFIG_SER_HWHANDSHAKE
01319         if (fifo_isfull(rxfifo))
01320             RTS_OFF;
01321 #endif
01322     }
01323     /* Re-enable receive complete int */
01324     //IRQ_DISABLE;
01325     //UCSR1B |= BV(RXCIE);
01326
01327     SER_STROBE_OFF;
01328 }
01329
01330 #endif // AVR_HAS_UART2
01331 
01332 #if AVR_HAS_UART3
01333 
01345 DECLARE_ISR(USART3_RX_vect)
01346 {
01347     SER_STROBE_ON;
01348
01349     /* Disable Recv complete IRQ */
01350     //UCSR1B &= ~BV(RXCIE);
01351     //IRQ_ENABLE;
01352
01353     /* Should be read before UDR */
01354     ser_handles[SER_UART3]->status |= UCSR3A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01355
01356     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01357      * not going to accept the incoming data
01358      */
01359     char c = UDR3;
01360     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART3]->rxfifo;
01361     //ASSERT_VALID_FIFO(rxfifo);
01362
01363     if (UNLIKELY(fifo_isfull(rxfifo)))
01364         ser_handles[SER_UART3]->status |= SERRF_RXFIFOOVERRUN;
01365     else
01366     {
01367         fifo_push(rxfifo, c);
01368 #if CONFIG_SER_HWHANDSHAKE
01369         if (fifo_isfull(rxfifo))
01370             RTS_OFF;
01371 #endif
01372     }
01373     /* Re-enable receive complete int */
01374     //IRQ_DISABLE;
01375     //UCSR1B |= BV(RXCIE);
01376
01377     SER_STROBE_OFF;
01378 }
01379
01380 #endif // AVR_HAS_UART3
01381 
01382
01386 DECLARE_ISR(SPI_STC_vect)
01387 {
01388     SER_STROBE_ON;
01389
01390     /* Read incoming byte. */
01391     if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
01392         fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
01393     /*
01394      * FIXME
01395     else
01396         ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
01397     */
01398
01399     /* Send */
01400     if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
01401         SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
01402     else
01403         UARTDescs[SER_SPI].sending = false;
01404
01405     SER_STROBE_OFF;
01406 }