00001
00044 #include <drv/timer_mega.h>
00045 #include <cfg/macros.h> // BV()
00046
00047 #include <cpu/types.h>
00048 #include <cpu/irq.h>
00049
00050 #include <avr/io.h>
00051
00052 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 \
00053     || CPU_AVR_ATMEGA88P || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P \
00054     || CPU_AVR_ATMEGA324P || CPU_AVR_ATMEGA644P
00055     #define REG_TIFR0 TIFR0
00056     #define REG_TIFR1 TIFR1
00057     #define REG_TIFR2 TIFR2
00058     #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00059         #define REG_TIFR3 TIFR3
00060     #endif
00061 
00062     #define REG_TIMSK0 TIMSK0
00063     #define REG_TIMSK1 TIMSK1
00064     #define REG_TIMSK2 TIMSK2
00065     #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00066         #define REG_TIMSK3 TIMSK3
00067     #endif
00068 
00069     #define REG_TCCR0A TCCR0A
00070     #define REG_TCCR0B TCCR0B
00071 
00072     #define REG_TCCR2A TCCR2A
00073     #define REG_TCCR2B TCCR2B
00074 
00075     #define REG_OCR0A  OCR0A
00076     #define REG_OCR2A  OCR2A
00077 
00078     #define BIT_OCF0A  OCF0A
00079     #define BIT_OCF2A  OCF2A
00080 
00081     #define BIT_OCIE0A OCIE0A
00082     #define BIT_OCIE2A OCIE2A
00083 #else
00084     #define REG_TIFR0 TIFR
00085     #define REG_TIFR1 TIFR
00086     #define REG_TIFR2 TIFR
00087     #define REG_TIFR3 TIFR
00088 
00089     #define REG_TIMSK0 TIMSK
00090     #define REG_TIMSK1 TIMSK
00091     #define REG_TIMSK2 TIMSK
00092     #define REG_TIMSK3 ETIMSK
00093 
00094     #define REG_TCCR0A TCCR0
00095     #define REG_TCCR0B TCCR0
00096 
00097     #define REG_TCCR2A TCCR2
00098     #define REG_TCCR2B TCCR2
00099 
00100     #define REG_OCR0A  OCR0
00101     #define REG_OCR2A  OCR2
00102 
00103     #define BIT_OCF0A  OCF0
00104     #define BIT_OCF2A  OCF2
00105 
00106     #define BIT_OCIE0A OCIE0
00107     #define BIT_OCIE2A OCIE2
00108 #endif
00109 
00110 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
00111     /* These ATMega have different prescaler options. */
00112     #define TIMER0_PRESCALER_64 BV(CS02)
00113     #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
00114 #else
00115     #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
00116     #define TIMER2_PRESCALER_64 BV(CS22)
00117 #endif
00118 
00120 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
00121 
00122     void timer_hw_init(void)
00123     {
00124         cpu_flags_t flags;
00125         IRQ_SAVE_DISABLE(flags);
00126
00127         /* Reset Timer flags */
00128         REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
00129
00130         /* Setup Timer/Counter interrupt */
00131         REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
00132         REG_TCCR0B = 0;
00133
00134         REG_TCCR0A = BV(WGM01);             /* Clear on Compare match */
00135             #if TIMER_PRESCALER == 64
00136             REG_TCCR0B |= TIMER0_PRESCALER_64;
00137             #else
00138                 #error Unsupported value of TIMER_PRESCALER
00139             #endif
00140 
00141         TCNT0 = 0x00;                 /* Initialization of Timer/Counter */
00142         REG_OCR0A = (uint8_t)OCR_DIVISOR;           /* Timer/Counter Output Compare Register */
00143
00144         /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
00145         REG_TIMSK0 &= ~BV(TOIE0);
00146         REG_TIMSK0 |= BV(BIT_OCIE0A);
00147
00148         IRQ_RESTORE(flags);
00149     }
00150
00151 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
00152 
00153     void timer_hw_init(void)
00154     {
00155         cpu_flags_t flags;
00156         IRQ_SAVE_DISABLE(flags);
00157
00158         /* Reset Timer overflow flag */
00159         REG_TIFR1 |= BV(TOV1);
00160
00161         /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
00162         #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
00163             TCCR1A |= BV(WGM11);
00164             TCCR1A &= ~BV(WGM10);
00165             TCCR1B |= BV(WGM12) | BV(CS10);
00166             TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
00167         /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
00168         #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
00169             TCCR1A |= BV(WGM10);
00170             TCCR1A &= ~BV(WGM11);
00171             TCCR1B |= BV(WGM12) | BV(CS10);
00172             TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
00173         #else
00174             #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
00175         #endif
00176 
00177         TCNT1 = 0x00;         /* initialization of Timer/Counter */
00178
00179         /* Enable timer interrupt: Timer/Counter1 Overflow */
00180         REG_TIMSK1 |= BV(TOIE1);
00181
00182         IRQ_RESTORE(flags);
00183     }
00184
00185 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
00186     void timer_hw_init(void)
00187     {
00188         cpu_flags_t flags;
00189         IRQ_SAVE_DISABLE(flags);
00190
00191         /* Reset Timer flags */
00192         REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
00193
00194         /* Setup Timer/Counter interrupt */
00195         REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
00196         REG_TCCR2B = 0; // ensure correct initialization.
00197
00198         REG_TCCR2A = BV(WGM21);
00199         #if TIMER_PRESCALER == 64
00200             REG_TCCR2B |= TIMER2_PRESCALER_64;
00201         #else
00202             #error Unsupported value of TIMER_PRESCALER
00203         #endif
00204 
00205         /* Clear on Compare match & prescaler = 64, internal sys clock.
00206            When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
00207         TCNT2 = 0x00;         /* initialization of Timer/Counter */
00208         REG_OCR2A = (uint8_t)OCR_DIVISOR;   /* Timer/Counter Output Compare Register */
00209
00210         /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
00211         REG_TIMSK2 &= ~BV(TOIE2);
00212         REG_TIMSK2 |= BV(BIT_OCIE2A);
00213
00214         IRQ_RESTORE(flags);
00215     }
00216
00217 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
00218 
00219     #if CPU_AVR_ATMEGA88P || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32 \
00220         || CPU_AVR_ATMEGA324P || CPU_AVR_ATMEGA644P
00221         #error For select target there is not TIMER_ON_OVERFLOW3, please select an other one.
00222     #endif
00223 
00224     void timer_hw_init(void)
00225     {
00226         cpu_flags_t flags;
00227         IRQ_SAVE_DISABLE(flags);
00228
00229         /* Reset Timer overflow flag */
00230         REG_TIFR3 |= BV(TOV3);
00231
00232         /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
00233         #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
00234             TCCR3A |= BV(WGM31);
00235             TCCR3A &= ~BV(WGM30);
00236             TCCR3B |= BV(WGM32) | BV(CS30);
00237             TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
00238         /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
00239         #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
00240             TCCR3A |= BV(WGM30);
00241             TCCR3A &= ~BV(WGM31);
00242             TCCR3B |= BV(WGM32) | BV(CS30);
00243             TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
00244         #else
00245             #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
00246         #endif
00247 
00248         /* initialization of Timer/Counter */
00249         TCNT3 = 0x00;
00250
00251         /* Enable timer interrupt: Timer/Counter3 Overflow */
00252         REG_TIMSK3 |= BV(TOIE3);
00253
00254         IRQ_RESTORE(flags);
00255     }
00256
00257 #else
00258     #error Unimplemented value for CONFIG_TIMER
00259 #endif /* CONFIG_TIMER */
00260